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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT564
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
FEATURES
• 3-state inverting outputs for bus oriented applications
• 8-bit positive-edge triggered register
• Common 3-state output enable input
• Independent register and 3-state buffer operation
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT564 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
74HC/HCT564
The 74HC/HCT564 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable
flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The “564” is functionally identical to the “574” but has
inverting outputs. The “564” is functionally identical to the
“534”, but has a different pinning.
(OE) input are common to all
SYMBOL PARAMETER CONDITIONS
t
PHL/ tPLH
f
max
C
I
C
PD
propagation delay CP to Q
n
CL= 15 pF; VCC=5 V 15 16 ns
maximum clock frequency 127 62 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per flip-flop notes 1 and 2 27 27 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
TYPICAL
UNIT
HC HCT
December 1990 2
Page 3
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge trigger;
74HC/HCT564
3-state; inverting
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
2, 3, 4, 5, 6, 7, 8, 9 D
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge-triggered)
19, 18, 17, 16, 15, 14, 13, 12
20 V
OE 3-state output enable input (active LOW)
to D
0
Q0 to Q
CC
7
7
data inputs
3-state flip-flop outputs
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
Page 4
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
FUNCTION TABLE
OPERATING
MODES
load and read
register
load register and
disable outputs
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH
CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH
CP transition
Z = high impedance OFF-state
↑ = LOW-to-HIGH clock transition
INPUTS
OE CP D
L
L
H
H
↑
↑
↑
↑
FLIP-FLOPS
n
l
h
l
h
74HC/HCT564
INTERNAL
L
H
L
H
OUTPUTS
Q0to Q
H
L
Z
Z
7
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990 4
Page 5
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PZH
/ t
/ t
propagation delay
PLH
CP to Q
3-state output enable
PZL
n
time
t
PHZ
OE to Q
/ t
3-state output disable
PLZ
n
time
t
THL
t
W
OE to Q
/ t
output transition time 14
TLH
clock pulse width
n
HIGH or LOW
t
su
set-up time
Dn to CP
t
h
hold time
Dn to CP
f
max
maximum clock pulse
frequency
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
T
min. typ. max. min. max. min. max.
50
165
18
33
14
28
44
140
16
28
13
24
50
135
18
27
14
23
60
5
12
4
10
80
14
16
5
14
4
60
6
12
2
10
2
5
0
5
0
5
0
6.0
38
30
115
35
137
amb
74HC
100
20
17
75
15
13
5
5
5
4.8
24
28
(°C)
205
41
35
175
35
30
170
34
29
75
15
13
120
24
20
90
18
15
5
5
5
4.0
20
24
250
50
43
210
42
36
205
41
35
90
18
15
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
74HC/HCT564
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
Fig.6
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.6
4.5
6.0
December 1990 5
Page 6
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge trigger;
74HC/HCT564
3-state; inverting
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
OE
D0 to D
CP
7
0.80
0.25
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
) for a unit load of 1 is given in the family specifications.
CC
.
SYMBOL PARAMETER
t
PHL
t
PZH
/ t
/ t
propagation delay
PLH
CP to Q
3-state output enable
PZL
n
time OE to Q
t
PHZ
/ t
3-state output disable
PLZ
time OE to Q
t
THL
t
W
/ t
output transition time 5 12 15 18 ns 4.5 Fig.6
TLH
clock pulse width
HIGH or LOW
t
su
set-up time
Dn to CP
t
h
hold time
Dn to CP
f
max
maximum clock pulse
frequency
T
amb
(°C)
TEST CONDITIONS
74HCT
UNIT
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
19 35 44 53 ns 4.5 Fig.6
19 35 44 53 ns 4.5 Fig.8
n
19 30 38 45 ns 4.5 Fig.8
n
18 8 23 27 ns 4.5 Fig.6
12 3 15 18 ns 4.5 Fig.7
3 −2 3 3 ns 4.5 Fig.7
27 56 22 18 MHz 4.5 Fig.6
December 1990 6
Page 7
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
74HC/HCT564
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.6 Waveforms showing the clock (CP) to
output (Qn) propagation delays, the clock
pulse width, the output transition times and
the maximum clock pulse frequency.
Fig.7 Waveforms showing the data set-up and
hold times for the data input (Dn).
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.8 Waveforms showing the 3-state enable and
disable times.
December 1990 7
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