Datasheet 74 hct563 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT563

Octal D-type transparent latch; 3-state; inverting

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product speciﬁcation

Octal D-type transparent latch; 3-state; inverting

FEATURES

• 3-state inverting outputs for bus oriented applications

• Inputs and outputs on opposite sides of package allowing easy interface with microprocessor

• Common 3-state output enable input

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT563 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT563 are octal D-type transparent latches featuring separate D-type inputs for each latch and inverting 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (

OE) input are common

to all latches. The “563” is functionally identical to

the “573”, but has inverted outputs. The “563” consists of eight D-type

transparent latches with 3-state inverting outputs. The LE and OE are

74HC/HCT563

common to all latches. When LE is HIGH, data at the D inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes.

When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.

n

SYMBOL PARAMETER CONDITIONS

t

PHL/ tPLH

C

I

C

PD

propagation delay Dn, LE to Q

n

input capacitance 3.5 3.5 pF power dissipation capacitance per latch notes 1 and 2 19 19 pF

CL= 15 pF; VCC=5 V 14 16 ns

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

for HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

TYPICAL

UNIT

HC HCT

December 1990 2

Philips Semiconductors Product speciﬁcation

Octal D-type transparent latch; 3-state; inverting

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

2, 3, 4, 5, 6, 7, 8, 9 D 11 LE latch enable input (active HIGH) 1 10 GND ground (0 V) 19, 18, 17, 16, 15, 14, 13, 12 20 V

to D

0

7

OE 3-state output enable input (active LOW)

Q0 to Q

7

CC

data inputs

3-state latch outputs positive supply voltage

74HC/HCT563

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product speciﬁcation

Octal D-type transparent latch; 3-state; inverting

Fig.4 Functional diagram.

74HC/HCT563

FUNCTION TABLE

OPERATING

MODES

enable and read register

latch and read register

latch register and disable outputs

Notes

1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the

HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the

HIGH-to-LOW LE transition Z = high impedance OFF-state

INPUTS

OE LE D

LLHHL

LLLLl

HHLLl

n

H

h

INTERNAL LATCHES

L

H

L

H

L

H

OUT-

PUTS

Q0to Q

H

L

H

L

Z Z

7

Fig.5 Logic diagram.

December 1990 4

Philips Semiconductors Product speciﬁcation

Octal D-type transparent latch; 3-state; inverting

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see Output capability: bus driver

ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

SYMBOL PARAMETER

/ t

t

PHL

PLH

t

/ t

PHL

PLH

t

/ t

PZH

PZL

= 6 ns; CL= 50 pF

r=tf

propagation delay

Dn to Q

n

propagation delay

LE to Q

n

3-state output enable time

t

PHZ

OE to Q

/ t

3-state output disable

PLZ

n

time

t

THL

t

W

OE to Q

/ t

output transition time 14

TLH

enable pulse width

n

HIGH

t

su

set-up time

Dn to LE

t

h

hold time

Dn to LE

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

min. typ. max. min. max. min. max.

47

145

17

29

14

25

47

145

17

29

14

25

47

150

17

30

14

26

50

150

18

30

14

26 60

5

12

4

10

80

14

16

5

14

4

50

11

10

4

9

3

4

−6

4

−2

4

−2

T

amb

74HC

100 20 17

65 13 11

4 4 4

(°C)

180 36 31

190 38 33

75 15 13

120 24 20

75 15 13

4 4 4

220 44 38

225 45 38

90 18 15

.

UNIT

ns 2.0

74HC/HCT563

TEST CONDITIONS

V

CC

WAVEFORMS+25 −40 to +85 −40 to +125

(V)

Fig.6

4.5

6.0 Fig.7

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.6

4.5

6.0 Fig.7

4.5

6.0 Fig.9

4.5

6.0 Fig.9

4.5

6.0

December 1990 5

Philips Semiconductors Product speciﬁcation

Octal D-type transparent latch; 3-state;

74HC/HCT563

inverting

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see Output capability: bus driver

ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

D LE OE

n

0.35

0.65

1.25

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

) for a unit load of 1 is given in the family specifications.

CC

.

SYMBOL PARAMETER

t

PHL

t

PHL

t

PZH

/ t

propagation delay

PLH

Dn to Q

propagation delay

PLH

LE to Q

3-state output enable

PZL

n

time OE to Q

t

PHZ

/ t

3-state output disable

PLZ

time OE to Q

t

THL

t

W

/ t

output transition time 5 12 15 18 ns 4.5 Fig.6

TLH

enable pulse width

HIGH

t

su

set-up time

Dn to LE

t

h

hold time

Dn to LE

T

amb

(°C)

TEST CONDITIONS

74HCT

UNIT

V

CC

WAVEFORMS+25 −40 to +85 −40 to +125

(V)

min. typ. max. min. max. min. max.

18 30 38 45 ns 4.5 Fig.6

19 35 44 53 ns 4.5 Fig.7

20 35 44 53 ns 4.5 Fig.8

n

22 35 44 53 ns 4.5 Fig.8

n

16 5 20 24 ns 4.5 Fig.7

10 3 13 15 ns 4.5 Fig.9

5 −1 5 5 ns 4.5 Fig.9

December 1990 6

Philips Semiconductors Product speciﬁcation

Octal D-type transparent latch; 3-state; inverting

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

74HC/HCT563

Fig.6 Waveforms showing the data input (Dn) to

output (Qn) propagation delays and the output transition times.

Fig.7 Waveforms showing the latch enable input

(LE) pulse width, the latch enable input to output (Qn) propagation delays and the output transition times.

The shaded areas indicate when the input is permitted to change for predictable output performance.

(1) HC : V

= 50%; VI= GND to VCC.

M

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.9 Waveforms showing the data set-up and

hold times for Dn input to LE input

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.8 Waveforms showing the 3-state enable and

disable times.

December 1990 7

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.