Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT533
Octal D-type transparent latch;
3-state; inverting
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
inverting
FEATURES
• 3-state inverting outputs for bus oriented applications
• Common 3-state output enable input
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT533 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT533 are octal D-type transparent latches
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (
latches.
OE) input are common to all
74HC/HCT533
The “533” consists of eight D-type transparent latches with
3-state inverting outputs. When LE is HIGH, data at the D
inputs enter the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its corresponding D-input changes.
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the 8 latches are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The “533” is functionally identical to the “373”, “563” and
“573”, but the “373” and “573” have non-inverted outputs
and the “563” and “573” have a different pin arrangement.
n
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/ tPLH
C
I
C
PD
propagation delay CL= 15 pF; VCC=5 V
D
to Q
n
n
Q
LE to
n
input capacitance 3.5 3.5 pF
power dissipation capacitance per latch notes 1 and 2 34 34 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
TYPICAL
UNIT
HC HCT
14 16 ns
18 19 ns
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
December 1990 2
.
Page 3
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
inverting
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18 D
10 GND ground (0 V)
11 LE latch enable input (active HIGH)
20 V
OE 3-state output enable input (active LOW)
Q0 to Q
to D
0
CC
7
7
3-state latch outputs
data inputs
positive supply voltage
74HC/HCT533
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
Page 4
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
inverting
Fig.4 Functional diagram.
74HC/HCT533
FUNCTION TABLE
OPERATING
MODES
enable and
read register
(transparent
mode)
latch and
read registerLLLLlh
latch register
and disable
outputs
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up prior to the
HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up prior to the
HIGH-to-LOW LE transition
X = don’t care
Z = high impedance OFF-state
INPUTS
OE LE D
LLHHL
HHXXX
n
H
X
INTERNAL
LATCHES
L
H
L
H
X
X
OUTPUTS
Q0 TO Q
H
L
H
L
Z
Z
7
Fig.5 Logic diagram (one latch).
Fig.6 Logic diagram.
December 1990 4
Page 5
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
inverting
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
PZH
/ t
/ t
/ t
propagation delay
PLH
Dn to Q
propagation delay
PLH
LE to Q
3-state output enable
PZL
n
n
time
t
PHZ
OE to Q
/ t
3-state output disable
PLZ
n
time
t
THL
t
W
OE to Q
/ t
output transition time 14
TLH
LE pulse width
n
HIGH
t
su
set-up time
Dn to LE
t
h
hold time
Dn to LE
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
min. typ. max. min. max. min. max.
47
150
17
30
14
26
58
175
21
35
17
30
44
150
16
30
13
26
50
150
18
30
14
26
60
5
12
4
10
80
14
16
5
14
4
50
3
10
1
9
1
35
3
7
1
6
1
T
amb
74HC
100
20
17
65
13
11
45
9
8
(°C)
190
38
33
220
44
37
190
38
33
190
38
33
75
15
13
120
24
20
75
15
13
55
11
9
225
45
38
265
53
45
225
45
38
225
45
38
90
18
15
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
74HC/HCT533
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.9
4.5
6.0
Fig.9
4.5
6.0
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.10
4.5
6.0
Fig.10
4.5
6.0
December 1990 5
Page 6
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
74HC/HCT533
inverting
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
D
LE
OE
n
0.15
0.30
0.55
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
) for a unit load of 1 is given in the family specifications.
CC
.
SYMBOL PARAMETER
t
PHL
t
PHL
t
PZH
/ t
/ t
/ t
propagation delay
PLH
Dn to Q
propagation delay
PLH
LE to Q
3-state output enable
PZL
n
n
time OE to Q
t
PHZ
/ t
3-state output disable
PLZ
time OE to Q
t
THL
t
W
/ t
output transition time 5 12 15 18 ns 4.5 Fig.7
TLH
LE pulse width
HIGH
t
su
set-up time
Dn to LE
t
h
hold time
Dn to LE
T
amb
(°C)
TEST CONDITIONS
74HCT
UNIT
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
19 34 43 51 ns 4.5 Fig.7
22 38 48 57 ns 4.5 Fig.8
19 35 44 53 ns 4.5 Fig.9
n
18 30 38 45 ns 4.5 Fig.9
n
16 5 20 24 ns 4.5 Fig.8
10 3 13 15 ns 4.5 Fig.10
8 2 10 12 ns 4.5 Fig.10
December 1990 6
Page 7
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
inverting
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
74HC/HCT533
Fig.7 Waveforms showing the data input (Dn) to
output (Qn) propagation delays and the
output transition times.
Fig.8 Waveforms showing the latch enable input
(LE) pulse width, the latch enable input to
output (Qn) propagation delays and the
output transition times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.10 Waveforms showing the data set-up and
hold times for Dn input to LE input.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.9 Waveforms showing the 3-state enable and
disable times.
December 1990 7
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
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