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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4520
Dual 4-bit synchronous binary
counter
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
FEATURES
• Output capability: standard
• ICC category: MSI
from all four bit positions (nQ0 to nQ3) and an active HIGH
overriding asynchronous master reset input (nMR).
The counter advances on either the LOW-to-HIGH
transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW
transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP
GENERAL DESCRIPTION
The 74HC/HCT4520 are high-speed Si-gate CMOS
devices and are pin compatible with the “4520” of the
“4000B” series. They are specified in compliance with
may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH
on nMR resets the counter (nQ0 to nQ3= LOW)
independent of nCP0 and nCP1.
JEDEC standard no. 7A.
The 74HC/HCT4520 are dual 4-bit internally synchronous
binary counters with an active HIGH clock input (nCP
0
and an active LOW clock input (nCP1), buffered outputs
APPLICATIONS
)
• Multistage synchronous counting
• Multistage asynchronous counting
• Frequency dividers
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
/ t
t
PHL
PLH
t
PHL
f
max
C
I
C
PD
propagation delay nCP0, nCP1 to nQ
propagation delay nMR to nQ
n
n
CL= 15 pF; VCC=5 V2424ns
maximum clock frequency 68 64 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per counter notes 1 and 2 29 24 pF
1
TYPICAL
UNIT
HC HCT
13 13 ns
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
December 1990 2
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Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 9 1CP
2, 10 1
3, 4, 5, 6 1Q
7, 15 1MR, 2MR asynchronous master reset inputs (active HIGH)
8 GND ground (0 V)
11, 12, 13, 14 2Q
16 V
, 2CP
0
CP1, 2CP
to 1Q
0
to 2Q
0
CC
clock inputs (LOW-to-HIGH, edge-triggered)
0
clock inputs (HIGH-to-LOW, edge-triggered)
1
3
3
data outputs
data outputs
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
FUNCTION TABLE
Fig.4 Functional diagram.
nCP
↑ H L counter advances
L ↓ L counter advances
↓ X L no change
X ↑ L no change
↑ L L no change
H ↓ L no change
XXHQ
Notes
1. H = HIGH voltage level
nCP1MR MODE
0
to Q3= LOW
0
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock transition
↓ = HIGH-to-LOW clock transition
Fig.5 Logic diagram (one counter).
Fig.6 Timing diagram.
December 1990 4
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Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
PHL
t
THL
t
W
/ t
/ t
/ t
propagation delay
PLH
nCP0 to nQ
propagation delay
PLH
nCP1 to nQ
n
n
propagation delay
nMR to nQ
output transition time 19
TLH
n
clock pulse width
HIGH or LOW
t
W
master reset pulse width
HIGH
t
t
rem
su
removal time
nMR to nCP0; nCP
set-up time
1
nCP1 to nCP0;
f
max
nCP0 to nCP
maximum clock pulse
1
frequency
(°C)
T
amb
74HC
min. typ. max. min. max. min. max.
77
80
16
14
120
24
20
0
0
0
80
16
14
6.0
30
35
28
22
77
28
22
44
16
13
7
6
22
8
6
39
14
11
−28
−10
−8
14
5
4
19
58
69
240
48
41
240
48
41
150
30
26
75
15
13
100
20
17
150
30
26
0
0
0
100
20
17
4.8
24
28
300
60
51
300
60
51
190
38
33
95
19
16
360
72
61
360
72
61
225
45
38
110
22
19
120
24
20
180
36
31
0
0
0
120
24
20
4.0
20
24
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.9
4.5
6.0
Fig.8
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.7
4.5
6.0
December 1990 5
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Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
nCP0, nCP
nMR
1
0.80
1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
T
amb
(°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
V
(V)
min. typ. max. min. max. min. max.
t
PHL
t
PHL
t
PHL
t
THL
/ t
/ t
/ t
propagation delay
PLH
nCP0 to nQ
propagation delay
PLH
nCP1 to nQ
n
n
propagation delay
nMR to nQ
output transition time 7 15 19 22 ns 4.5 Fig.8
TLH
n
28 53 66 80 ns 4.5 Fig.8
25 53 66 80 ns 4.5 Fig.8
16 35 44 53 ns 4.5 Fig.9
CC
WAVEFORMS+25 −40 to +85 −40 to +125
t
W
clock pulse width
20 10 25 30 ns 4.5 Fig.7
HIGH or LOW
t
W
master reset pulse width
20 12 25 30 ns 4.5 Fig.7
HIGH
t
t
rem
su
removal time
nMR to nCP0; nCP
set-up time
0 −8 0 0 ns 4.5 Fig.7
1
16 6 20 24 ns 4.5 Fig.8
nCP1 to nCP0;
f
max
nCP0 to nCP
maximum clock pulse
1
30 58 24 20 MHz 4.5 Fig.7
frequency
December 1990 6
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Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
AC WAVEFORMS
Conditions:
CP1= HIGH while nCP0 is triggered on a LOW-to-HIGH transition; t
n
and t
also apply when nCP0= LOW and nCP1 is triggered on a
rem
HIGH-to-LOW transition.
(1) HC : V
= 50%; VI = GND to V
M
HCT: VM = 1.3 V; VI = GND to 3 V.
CC.
Fig.7 Waveforms showing removal time for nMR; minimum nCP0, nCP1, nMR pulse widths and maximum clock
pulse frequency.
W
(1) HC : VM = 50%; VI = GND to V
HCT: VM = 1.3 V; VI = GND to 3 V.
CC.
Fig.8 Waveforms showing set-up times for nCP0 to nCP1 and nCP1 to nCP0, propagation delays and output
transition times.
(1) HC : VM = 50%; VI = GND to V
HCT: VM = 1.3 V; VI = GND to 3 V.
CC.
Fig.9 Waveforms showing propagation delay from nMR to nQn output.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 7
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