Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4516
Binary up/down counter
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
FEATURES
• Output capability: standard
• ICC category: MSI
parallel load input (PL), four parallel inputs (D0 to D3), four
parallel outputs (Q0 to Q3), an active LOW terminal count
output (TC), and an overriding asynchronous master reset
input (MR).
Information on D0 to D3 is loaded into the counter while PL
GENERAL DESCRIPTION
The 74HC/HCT4516 are high-speed Si-gate CMOS
devices and are pin compatible with the “4516” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4516 are edge-triggered synchronous
up/down 4-bit binary counters with a clock input (CP), an
up/down count control input (UP/
DN), an active LOW
is HIGH, independent of all other input conditions except
the MR input, which must be LOW. When PL and CE are
LOW, the counter changes on the LOW-to-HIGH transition
of CP. UP/DN determines the direction of the count, HIGH
for counting up, LOW for counting down. When counting
up, TC is LOW when Q0 to Q3 are HIGH and CE is LOW.
When counting down, TC is LOW when Q0 to Q3 and CE
are LOW. A HIGH on MR resets the counter (Q0 to
Q3= LOW) independent of all other input conditions.
count enable input (CE), an asynchronous active HIGH
Logic equation for terminal count:
TC = CE .{(UP/DN).Q0.Q1.Q2.Q3+(UP DN⁄ ).Q0.Q1.Q2.Q3}
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
f
max
C
C
I
PD
/ t
PLH
propagation delay CP to Q
maximum clock frequency 45 57 MHz
n
CL= 15 pF; VCC=5 V
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 59 61 pF
TYPICAL
UNIT
HC HCT
19 19 ns
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
December 1990 2
.
Page 3
Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1 PL parallel load input (active HIGH)
4, 12, 13, 3 D
5
6, 11, 14, 2 Q
7
8 GND ground (0 V)
9 MR asynchronous master reset input (active HIGH)
10 UP/
15 CP clock input (LOW-to-HIGH, edge-triggered)
16 V
to D
0
3
parallel inputs
CE count enable input (active LOW)
to Q
0
3
parallel outputs
TC terminal count output (active LOW)
DN up/down control input
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Fig.3 IEC logic symbol.
December 1990 3
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Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
FUNCTION TABLE
Fig.4 Functional diagram.
MR PL UP/
L
L
L
L
H
Notes
1. H = HIGH voltage level
H
L
L
L
X
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock transition
DN CE CP MODE
X
X
L
H
X
X
X
parallel load
H
X
no change
L
↑
count down
L
↑
count up
X
X
reset
Fig.5 Timing diagram.
December 1990 4
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Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
Fig.6 Logic diagram.
December 1990 5
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Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
PLH
t
PHL
/ t
/ t
/ t
propagation delay
PLH
CP to Q
propagation delay
MR to Q
propagation delay
PHL
PL to Q
propagation delay
PLH
n
n
n
CP to TC
t
PHL
/ t
propagation delay
PLH
CE to TC
t
PLH
propagation delay
MR to TC
t
PLH
/ t
propagation delay
PHL
PL to TC
t
TLH
t
W
/ t
output transition time 19
THL
clock pulse width CP,
CE HIGH or LOW
t
W
parallel load pulse
width HIGH
t
W
master reset pulse
width HIGH
(°C)
T
amb
74HC
min. typ. max. min. max. min. max.
72
80
16
14
80
16
14
80
16
14
26
21
69
25
20
83
30
24
74
27
22
36
13
10
69
25
20
91
33
26
7
6
25
9
7
28
10
8
19
7
6
220
44
37
210
42
36
250
50
43
260
52
44
125
25
21
235
47
40
300
60
51
75
15
13
100
20
17
100
20
17
100
20
17
275
55
47
265
53
45
315
63
54
325
65
55
155
31
26
295
59
50
375
75
64
95
19
16
330
66
56
315
63
54
375
75
64
395
78
66
190
38
32
355
71
60
450
90
77
110
22
19
120
24
20
120
24
20
120
24
20
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to+85 −40 to +125
(V)
Fig.7
4.5
6.0
Fig.10
4.5
6.0
Fig.9
4.5
6.0
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.10
4.5
6.0
Fig.9
4.5
6.0
Fig.9
4.5
6.0
Fig.7
4.5
6.0
Fig.10
4.5
6.0
Fig.10
4.5
6.0
December 1990 6
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Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
T
SYMBOL PARAMETER
t
rem
removal time
MR to CP
t
rem
removal time
PL to CP
t
su
set-up time
UP/DN to CP
t
su
set-up time
CE to CP
t
su
set-up time
Dn to PL
t
h
hold time
CE to CP
t
h
hold time
Dn to PL
t
h
hold time
UP/DN to CP
f
max
maximum clock pulse
frequency
(°C)
amb
74HC
min. typ. max. min. max. min. max.
80
16
14
80
16
14
100
20
17
100
20
17
100
20
17
5
5
5
3
3
3
0
0
0
6.0
30
35
28
10
8
25
9
7
30
11
9
19
7
6
17
6
5
0
0
0
−6
−2
−2
−19
−7
−6
16
49
58
100
20
17
100
20
17
125
25
21
125
25
21
125
25
21
5
5
5
3
3
3
0
0
0
4.8
24
28
120
24
20
120
24
20
150
30
26
150
30
26
150
30
26
5
5
5
3
3
3
0
0
0
4.0
20
24
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to+85 −40 to +125
(V)
Fig.10
4.5
6.0
Fig.10
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.11
4.5
6.0
Fig.8
4.5
6.0
Fig.11
4.5
6.0
Fig.8
4.5
6.0
Fig.7
4.5
6.0
December 1990 7
Page 8
Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆I
INPUT UNIT LOAD COEFFICIENT
D
n
PL, CE
UP/DN
CP
MR
per input, multiply this value by the unit load coefficient shown in the table below.
CC
0.75
1.00
1.00
1.25
1.50
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
December 1990 8
Page 9
Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
PLH
t
PHL
/ t
PLH
/ t
PHL
/ t
PLH
propagation delay
CP to Q
n
propagation delay
MR to Q
n
propagation delay
PL to Q
n
propagation delay
CP to TC
t
PHL
/ t
PLH
propagation delay
CE to TC
t
PLH
propagation delay
MR to TC
t
PLH
/ t
PHL
propagation delay
PL to TC
t
TLH
t
W
/ t
THL
output transition time 7 15 19 22 ns 4.5 Fig.9
clock pulse width CP,
CE HIGH or LOW
t
W
parallel load pulse
width HIGH
t
W
master rest pulse
width HIGH
t
rem
removal time
MR to CP
t
rem
removal time
PL to CP
t
su
set-up time
UP/DN to CP
t
su
set-up time
CE to CP
t
su
set-up time
Dn to PL
t
h
hold time
CE to CP
T
amb
(°C)
TEST CONDITIONS
74HCT
UNIT
V
(V)
CC
WAVEFORMS+25 −40 to +85 −40 to+125
min. typ. max. min. max. min. max.
28 50 63 75 ns 4.5 Fig.7
24 42 53 63 ns 4.5 Fig.10
32 53 66 80 ns 4.5 Fig.9
29 58 73 87 ns 4.5 Fig.7
18 31 39 47 ns 4.5 Fig.8
31 50 63 75 ns 4.5 Fig.10
34 68 85 102 ns 4.5 Fig.9
16 9 20 24 ns 4.5 Fig.7
16 8 20 24 ns 4.5 Fig.10
20 5 25 30 ns 4.5 Fig.10
23 14 29 35 ns 4.5 Fig.10
17 10 21 26 ns 4.5 Fig.10
20 11 25 30 ns 4.5 Fig.8
20 9 25 30 ns 4.5 Fig.8
20 9 25 30 ns 4.5 Fig.11
10 9 13 15 ns 4.5 Fig.8
December 1990 9
Page 10
Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
T
SYMBOL PARAMETER
t
h
hold time
Dn to PL
t
h
hold time
UP/DN to CP
f
max
maximum clock pulse
frequency
(°C)
amb
74HCT
UNIT
min. typ. max. min. max. min. max.
5 −6 5 5 ns 4.5 Fig.11
0 −5 0 0 ns 4.5 Fig.8
30 52 24 20 MHz 4.5 Fig.7
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to +85 −40 to+125
(V)
December 1990 10
Page 11
Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
AC WAVEFORMS
(1) HC : V
HCT: V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
Fig.7 Waveforms showing the clock (CP) to
output (Qn) and terminal count (TC)
propagation delays, the clock pulse width
and the maximum clock pulse frequency.
(1) HC : V
HCT: V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
Fig.8 Waveforms showing the set-up and hold
times form count enable (CE) and up/down
(UP/DN) control inputs to the clock pulse
(CP), the propagation delays from UP/DN,
CE to TC.
(1) HC : V
HCT: V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
Fig.9 Waveforms showing the preset enable
pulse width, preset enable to output
delays and output transition times.
December 1990 11
(1) HC : V
HCT: V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
Fig.10 Waveforms showing the master reset pulse,
master reset to terminal count and Q
n
delay and master reset to clock removal
time.
Page 12
Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
(1) HC : V
HCT: V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
Fig.11 Waveforms showing the data set-up and hold times to parallel load (PL).
December 1990 12
Page 13
Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
APPLICATION INFORMATION
Terminal count (TC) lines at the 2nd, 3rd, etc. Stages may have a negative-going glitch pulse resulting from differential
delays of different 4516s. These negative-going glitches do not affect proper 4516 operation. However, if the terminal
count signals are used to trigger other edge-sensitive logic devices, such as flip-flops or counters, the terminal count
signals should be gated with the clock signal using a 2-input OR gate such as HC/HCT32.
Fig.12 Cascading counter packages (parallel clocking).
Ripple clocking mode: the UP/DN control can be changed at any count. The only restriction on changing the
DN control is that the clock input to the first counting stage must be “HIGH”. For cascading counters operating in a
UP/
fixed up-count or down-count mode, the OR gates are not required between stages and
CP input of the next stage with
CE grounded.
TC is connected directly to the
Fig.13 Cascading counter packages (ripple clocking).
December 1990 13
Page 14
Philips Semiconductors Product specification
Binary up/down counter 74HC/HCT4516
Use the following formulae to calculate
:
N
total
i
N
total
f
out=fin/Ntotal
16 N
π
1
N
×()
+=
i
0
Fig.14 State diagram.
parallel inputs
D
D
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Note
1. no count; f
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
is HIGH.
out
Fig.15 Programmable cascaded frequency divider.
PACKAGE OUTLINES
See
count-upncount-down
D
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(1)
n
(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 14
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