Datasheet 74 hct4066 DATASHEETS (Philips)

Page 1
INTEGRATED CIRCUITS
DATA SH EET
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
74HC/HCT4066
Quad bilateral switches
Product specification Supersedes data of 1998 Oct 02 File under Integrated Circuits, IC06
1998 Nov 10
Page 2
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066

FEATURES

• Very low “ON” resistance: 50 Ω (typ.) at VCC= 4.5 V 45 Ω (typ.) at VCC= 6.0 V 35 Ω (typ.) at VCC= 9.0 V
• Output capability: non-standard
• ICC category: SSI.
The 74HC/HCT4066 have four independent analog switches. Each switch has two input/output terminals (nY, nZ) and an active HIGH enable input (nE). When nE is LOW the belonging analog switch is turned off.
The “4066” is pin compatible with the “4016” but exhibits a much lower “ON” resistance. In addition, the “ON” resistance is relatively constant over the full input signal range.

GENERAL DESCRIPTION

The 74HC/HCT4066 are high-speed Si-gate CMOS devices and are pin compatible with the “4066” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T
=25°C; tr=tf=6ns
amb
SYMBOL PARAMETER CONDITIONS
t
PZH
t
PHZ
C C C
I PD S
/ t
PZL
/ t
PLZ
turn-on time nE to V turn-off time nE to V
os os
CL= 15 pF; RL=1kΩ; VCC= 5 V 11 12 ns
input capacitance 3.5 3.5 pF power dissipation capacitance per switch notes 1 and 2 11 12 pF max. switch capacitance 8 8 pF
TYPICAL
UNIT
HC HCT
13 16 ns
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
a) PD=CPD× V
2
× fi+∑{(CL+ CS)×V
CC
b) fi= input frequency in MHz c) fo= output frequency in MHz d) ∑ {(CL+ CS)×V
2
× fo} = sum of outputs
CC
e) CL= output load capacitance in pF f) CS= maximum switch capacitance in pF g) VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
2
× fo} where:
CC
1998 Nov 10 2
Page 3
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066

ORDERING INFORMATION

TYPE
NUMBER
NAME DESCRIPTION VERSION
PACKAGE
74HC4066 DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HC4066 SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HC4066 SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74HC4066 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HCT4066 DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HCT4066 SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HCT4066 SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74HCT4066 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION
1, 4, 8, 11 1Y to 4Y independent inputs/outputs 2, 3, 9, 10 1Z to 4Z independent inputs/outputs 7 GND ground (0 V) 13, 5, 6, 12 1E to 4E enable inputs (active HIGH) 14 V
CC
positive supply voltage
handbook, halfpage
1Y 1Z 2Z 2Y 2E 3E
GND
1 2 3 4
4066
5 6 7
MGR253
14
V
CC
13
1E
12
4E
11
4Y
10
4Z
9
3Z
8
3Y
Fig.1 Pin configuration.
1998 Nov 10 3
handbook, halfpage
1E
13
52E
63E
12 4E
MGR254
Fig.2 Logic symbol.
11Y 21Z
42Y 32Z
83Y 93Z
114Y 104Z
Page 4
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
handbook, halfpage
1 13 # 4 5# 8 6# 11 12 #
2
3
9
10
MGR255
handbook, halfpage
a. b.
Fig.3 IEC logic symbol.

FUNCTION TABLE

INPUT NE SWITCH
Loff
Hon
1
11
13 #
X1
4
11
5#
X1
8
11
6#
X1
11
11
12 #
X1
2
3
9
10
MGR256
handbook, halfpage
13 1E
1Y
1Z 2
2E
2Y
2Z 3
3E
3Y
3Z 9
4E
4Y
4Z 10
MGR257
11
12
8
6
4
5
1
Fig.4 Functional diagram.
1998 Nov 10 4
Note
1. H = HIGH voltage level; L = LOW voltage level.
handbook, halfpage
nE
V
GND
CC
nY
V
CC
nZ
MGR258
Fig.5 Schematic diagram (one switch).
Page 5
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (GND=0V)
SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS
V
CC
±I
IK
±I
SK
±I
IS
±I
CC;
±I
GND
T
stg
P
tot
P
S
DC supply voltage −0.5 +11.0 V DC digital input diode current 20 mA for VI<−0.5 V or VI> VCC+ 0.5 V DC switch diode current 20 mA for VS<−0.5 V or VS> VCC+ 0.5 V DC switch current 25 mA for −0.5 V < VS< VCC+ 0.5 V DC VCCor GND current 50 mA
storage temperature range −65 +150 °C power dissipation per package for temperature range: −40 to +125 °C
74HC/HCT plastic DIL 750 mW above +70 °C: derate linearly with 12 mW/K plastic mini-pack (SO) 500 mW above +70 °C: derate linearly with 8 mW/K power dissipation per switch 100 mW
Note
1. To avoid drawing V
current out of terminal nZ, when switch current flows in terminal nY, the voltage drop across
CC
the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCCcurrent will flow out of terminal nY. In this case there is no limit for the voltage drop across the switch, but the voltages at nY and nZ may not exceed VCCor GND.

RECOMMENDED OPERATING CONDITIONS

74HC 74HCT
SYMBOL PARAMETER
UNIT CONDITIONS
min. typ. max. min. typ. max.
V
CC
V
I
V
S
T
amb
T
amb
DC supply voltage 2.0 5.0 10.0 4.5 5.0 5.5 V DC input voltage range GND V DC switch voltage range GND V operating ambient
−40 +85 −40 +85 °C see DC and AC
GND V
CC
GND V
CC
CC CC
temperature range operating ambient
−40 +125 −40 +125 °C
V V
CHARACTERISTICS
temperature range
t
r,tf
input rise and fall times 6.0 1000 6.0 500 ns VCC= 2.0 V
500 V 400 V 250 V
= 4.5 V
CC
= 6.0 V
CC
= 10.0 V
CC
1998 Nov 10 5
Page 6
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066

DC CHARACTERISTICS FOR 74HC/HCT

For 74HC: V
SYMBOL PARAMETER
R
ON
R
ON
R
ON
∆R
ON
= 2.0, 4.5, 6.0 and 9.0 V; For 74HCT: VCC= 4.5 V
CC
T
amb
(°C)
TEST CONDITIONS
74HC/HCT
+25 −40 to +85 −40 to +125
V
CC
(V)
I
S
(µA)
V
IS
UNIT
min. typ. max. min. max. min. max.
ON-resistance (peak) −− − − Ω 2.0 100 V
54 95 118 142 Ω 4.5 1000 42 84 105 126 Ω 6.0 1000
CC
to GND
32 70 88 105 Ω 9.0 1000
ON-resistance (rail) 80 −−−Ω2.0 100 GND V
35 75 95 115 Ω 4.5 1000 27 65 82 100 Ω 6.0 1000 20 55 70 85 Ω 9.0 1000
ON-resistance (rail) 100 −−−Ω2.0 100 V
CCVIH
42 80 106 128 Ω 4.5 1000 35 75 94 113 Ω 6.0 1000 27 60 78 95 Ω 9.0 1000
maximum variation of ON-resistance between any two channels
−Ω2.0 V 5 Ω 4.5 4 Ω 6.0
CC
to GND
3 Ω 9.0
V or V
or V
or V
V or V
V
I
IH
IL
IH
IL
IL
IH
IL
Note
1. At supply voltages approaching 2 V, the analog switch ON-resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital signals only, when using these supply voltages.
1998 Nov 10 6
Page 7
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
book, full pagewidth
handbook, full pagewidth
HIGH
(from enable inputs)
V
= 0 to VCC − GND
is
(from enable inputs)
VI = VCC or GND
V
nY
MGR259
nZ
I
is
GND
Fig.6 Test circuit for measuring ON-resistance (RON).
LOW
nY
nZ
MGR260
AA
GND
VO = GND or V
CC
Fig.7 Test circuit for measuring OFF-state current.
handbook, full pagewidth
VI = VCC or GND
HIGH
(from enable inputs)
nY
Fig.8 Test circuit for measuring ON-state current.
1998 Nov 10 7
nZ
MGR261
AA
GND
VO (open circuit)
Page 8
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
60
handbook, halfpage
R
ON
(Ω)
50
40
30
20
10
09
VCC = 4.5 V
6 V
1.8 3.6 5.4 7.2
MGR262
9 V
Vis (V)
Fig.9 Typical ON-resistance (RON) as a function of input voltage (Vis) for Vis= 0 to VCC.
1998 Nov 10 8
Page 9
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066

DC CHARACTERISTICS FOR 74HC

Voltage are referenced to GND (ground = 0 V)
T
SYMBOL PARAMETER
V
IH
HIGH-level input voltage
V
IL
LOW-level input voltage
±I
I
input leakage current
±I
S
analog switch OFF-state current per channel
±I
S
analog switch ON-state current
I
CC
quiescent supply current
(°C)
amb
74HC
+25 −40 to +85
−40 to
+125
UNIT
min. typ. max. min. max. min. max
1.5 1.2 1.5 1.5 V 2.0
3.15 2.4 3.15 3.15 4.5
4.2 3.2 4.2 4.2 6.0
6.3 4.7 6.3 6.3 9.0
0.8 0.50 0.50 0.50 V 2.0
2.1 1.35 1.35 1.35 4.5
2.8 1.80 1.80 1.80 6.0
4.3 2.70 2.70 2.70 9.0
0.1 1.0 1.0 µA 6.0 V
0.2 2.0 2.0 10.0
0.1 1.0 1.0 µA 10.0 V
0.1 1.0 1.0 µA 10.0 V
2.0 20.0 40.0 µA 6.0 V
4.0 40.0 80.0 10.0
TEST CONDITIONS
V
V
CC
I
(V)
CC
or GND
VS=VCC− GND
IH
or
(see Fig.7)
V
IL
VS=VCC− GND
IH
or
(see Fig.8)
V
IL
Vis= GND or
CC
or
VCC;
GND
Vos=VCCor GND
OTHER
1998 Nov 10 9
Page 10
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t
SYMBOL PARAMETER
t
PHL/tPLH
t
PZH/tPZL
t
PHZ/tPLZ
= 6 ns; CL=50pF
r=tf
propagation delay Visto V
os
turn-on time nE to V
os
turn-off time nE to V
os
T
(°C)
amb
74HC
+25 −40 to +85 −40 to +125
UNIT
V
(V)
CC
min. typ. max. min. max. min. max.
8 60 75 90 ns 2.0 RL= ∞; 3 12 15 18 4.5 2 10 13 15 6.0 2 8 10 12 9.0 36 100 125 150 ns 2.0 RL=1kΩ; 13 20 25 30 4.5 10 17 21 26 6.0 8 13 16 20 9.0 44 150 190 225 ns 2.0 RL=1kΩ; 16 30 38 45 4.5 13 26 33 38 6.0 16 24 16 20 9.0
TEST CONDITIONS
OTHER
CL=50pF (see Fig.18)
CL=50pF (see Figs 19 and 20)
CL=50pF (see Figs 19 and 20)
1998 Nov 10 10
Page 11
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066

DC CHARACTERISTICS FOR 74HCT

Voltages are referenced to GND (ground = 0 V)
T
SYMBOL PARAMETER
V
IH
HIGH-level input voltage
V
IL
LOW-level input voltage
±I
I
input leakage current
±I
S
analog switch OFF-state current per channel
±I
S
analog switch ON-state current
I
CC
quiescent supply current
∆I
CC
additional quiescent supply current per input pin for unit load coefficient is 1 (note 1)
(°C)
amb
74HCT
UNIT
min. typ. max. min. max. min. max.
2.0 1.6 2.0 2.0 V 4.5
1.2 0.8 0.8 0.8 V 4.5
0.1 1.0 1.0 µA 5.5 V
0.1 1.0 1.0 µA 5.5 V
0.1 1.0 1.0 µA 5.5 V
2.0 20.0 40.0 µA 4.5
100 360 450 490 µA 4.5
TEST CONDITIONS
V
CC
V
(V)
I
to
5.5
to
5.5
CC
or GND
IH
or V
IL
IH
or V
IL
V
CC
to
or
5.5
GND VCC−
to
2.1 V
5.5
OTHER+25 −40 to +85 −40 to +125
VS=VCC− GND (see Fig.7)
VS=VCC− GND (see Fig.8)
Vis= GND or VCC; Vos=VCCor GND
other inputs at VCCor GND
Note
1. The value of additional quiescent supply current (∆I
) for a unit load of 1 is given here. To determine ∆ICC per input,
CC
multiply this value by the unit load coefficient shown in the table below.
Table 1
INPUT UNIT LOAD COEFFICIENT
nE 1.00
1998 Nov 10 11
Page 12
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t
r=tf
=6ns
(°C)
T
amb
74HCT
SYMBOL PARAMETER
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL/tPLH
t
PZH/tPZL
t
PHZ/tPLZ
propagation delay Visto V
turn-on time nE to V
os
turn-off time nE to V
os
3 12 15 18 ns 4.5 RL= ∞;CL=50pF
os
12 24 30 36 ns 4.5 RL=1kΩ; CL=50pF
20 35 44 53 ns 4.5 RL=1kΩ; CL=50pF

ADDITIONAL AC CHARACTERISTICS FOR 74HC/HCT

Recommended conditions and typical values GND = 0 V; t
SYMBOL PARAMETER TYP. UNIT
sine wave distortion f = 1 kHz 0.04 % 4.5 4.0 R
0.02 % 9.0 8.0
sine wave distortion f = 10 kHz 0.12 % 4.5 4.0 R
0.06 % 9.0 8.0
switch “OFF” signal feed-through −50 dB 4.5 note 3 RL= 600 Ω; CL= 50 pF;
−50 dB 9.0
V
(p−p)
crosstalk between any two switches
crosstalk voltage between enable or address input to any switch
−60 dB 4.5 note 3 R
−60 dB 9.0
110 mV 4.5 RL= 600 Ω; CL= 50 pF; 220 mV 9.0
(peak-to-peak value)
f
max
C
minimum frequency response (−3 dB)
S
maximum switch capacitance 8 pF
180 MHz 4.5 note 4 RL=50Ω; CL=10pF 200 MHz 9.0
r=tf
=6ns
V
CC
(V)
V
IS(p−p)
(V)
TEST CONDITIONS
UNIT
V
CC
OTHER
(V)
(see Fig.18)
(see Figs 19 and 20)
(see Figs 19 and 20)
CONDITIONS
=10kΩ; CL=50pF
L
(see Fig.16)
=10kΩ; CL=50pF
L
(see Fig.16)
f = 1 MHz (see Figs 10 and 17)
= 600 Ω; CL= 50 pF;
L
f = 1 MHz (see Fig.12)
f = 1 MHz (nE, square wave between VCC and GND, tr=tf= 6 ns) (see Fig.14)
(see Figs 11 and 15)
Notes
1. V
is the input voltage at nY or nZ terminal, whichever is assigned as an input.
is
2. Vosis the output voltage at nY or nZ terminal, whichever is assigned as an output.
3. Adjust input voltage Visis 0 dBM level (0 dBM = 1 mW into 600 Ω).
4. Adjust input voltage Visis 0 dBM level at Vosfor 1 MHz (0 dBM = 1 mW into 50 Ω).
1998 Nov 10 12
Page 13
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
handbook, full pagewidth
0
(dB)
−20
−40
−60
−80
−100
10 10
2
Test conditions: VCC= 4.5 V; GND = 0 V; RL=50Ω; R
Fig.10 Typical switch “OFF” signal feed-through as a function of frequency.
source
3
10
=1kΩ.
MGR263
4
10
5
10
f (kHz)
6
10
handbook, full pagewidth
5
(dB)
0
−5 10 10
2
Test conditions: VCC= 4.5 V; GND = 0 V; RL=50Ω; R
source
3
10
=1kΩ.
4
10
Fig.11 Typical frequency response.
MGR264
5
10
f (kHz)
6
10
1998 Nov 10 13
Page 14
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
handbook, full pagewidth
Fig.12 Test circuit for measuring crosstalk between any two switches; channel ON condition.
handbook, full pagewidth
V
0.1 µF
i
2R
V
CC
2R
L
R
L
channel
ON
V
CC
2R
L
L
channel
OFF
V
CC
2R
L
2R
L
2R
L
CLdB
nZ/nYnY/nZ
C
L
MGM265
nZ/nYnY/nZ
MGR266
GND
V
os
GND
Fig.13 Test circuit for measuring crosstalk between any two switches; channel OFF condition.
The crosstalk is defined as follows (oscilloscope output):
page
handbook, full pagewidth
V(p-p)
MGR267
Fig.14 Test circuit for measuring crosstalk between control and any switch.
1998 Nov 10 14
V
CC
GND
2R
V
CC
2R
L
C
L
L
nZ/nYnY/nZ
oscilloscope
MGR268
V
os
GND
V
CC
2R
L
2R
nE
D.U.T.
L
Page 15
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
handbook, full pagewidth
0.1 µF
V
sine-wave
Adjust input voltage to obtain 0 dBM at Voswhen fin= 1 MHz. After set-up frequency of finis increased to obtain a reading of −3 dB at Vos.
is
channel
ON
V
CC
2R
L
2R
CLdB
L
nZ/nYnY/nZ
MGR269
V
os
GND
Fig.15 Test circuit for measuring minimum frequency response.
handbook, full pagewidth
fin = 1 kHz sine-wave
10 µF
V
is
channel
ON
V
CC
2R
L
DISTORTION
2R
C
L
L
METER
nZ/nYnY/nZ
MGR270
V
os
GND
Fig.16 Test circuit for measuring sine wave distortion.
handbook, full pagewidth
V
0.1 µF
is
channel
OFF
V
CC
Fig.17 Test circuit for measuring switch “OFF” signal feed-through.
1998 Nov 10 15
2R
L
2R
CLdB
L
nZ/nYnY/nZ
MGR271
V
os
GND
Page 16
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066

AC WAVEFORMS

10%
t
r
90%
50%
50%
handbook, full pagewidth
V
is
V
os
(1) HC: VM= 50%; VI= GND to VCC; HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.18 Waveforms showing the input (Vis) to output (Vos) propagation delays.
t
f
90 %
nE INPUT
OUTPUT LOW - to - OFF OFF - to - LOW
OUTPUT HIGH - to - OFF OFF - to - HIGH
MGA846
(1)
V
M
t
PLH
10 %
t
PLZ
t
PHZ
outputs enabled
10 %
90 %
t
f
t
PHL
outputs
disabled
V
CC
GND
MGR272
t
r
t
PZL
50 %
t
PZH
50 %
outputs enabled
Fig.19 Waveforms showing the turn-on and turn-off times.

TEST CIRCUIT AND WAVEFORMS

V
handbook, full pagewidth
PULSE
GENERATOR
V
I
V
CC
is
D.U.T.
R
T
Fig.20 Test circuit for measuring AC performance.
1998 Nov 10 16
V
CC
V
O
switch
R
L
C
L
open
GND
MGR273
Page 17
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
Table 2 Conditions
TEST SWITCH V
t
PZH
t
PZL
t
PHZ
t
PLZ
GND V
V
CC
GND V
V
CC
others open pulse
Table 3 Definitions for Figs 20 and 21:
SYMBOL DEFINITION
C
L
R
T
t
r
handbook, full pagewidth
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values) termination resistance should be equal to the output impedance ZOof the pulse generator tf= 6 ns, when measuring f
NEGATIVE
INPUT PULSE
POSITIVE
INPUT PULSE
90%
10%
, there is no constraint on tr, tfwith 50% duty factor
max
t
W
V
M 10%
t
(tf)t
THL
t
(tr)t
TLH
90%
V
M
t
W
TLH THL
IS
CC
GND
CC
GND
AMPLITUDE
0 V
(tr) (tf)
AMPLITUDE
0 V
MGR274
Fig.21 Input pulse definitions.
Table 4
FAMILY AMPLITUDE V
74HC V
CC
74HCT 3.0 V 1.3 V < 2ns 6ns
1998 Nov 10 17
tr;t
f
M
f
;
max
PULSE WIDTH
OTHER
50% < 2ns 6ns
Page 18
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066

PACKAGE OUTLINES

DIP14: plastic dual in-line package; 14 leads (300 mil)
D
seating plane
L
Z
14
pin 1 index
e
b

SOT27-1

M
E
A
2
A
A
1
w M
b
1
8
E
c
(e )
1
M
H
1
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
A
A
UNIT
inches
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
max.
mm
OUTLINE
VERSION
SOT27-1
1 2
min.
max.
1.73
1.13
0.068
0.044
IEC JEDEC EIAJ
050G04 MO-001AA
b
b
1
0.53
0.38
0.021
0.015
0.014
0.009
REFERENCES
cD
0.36
0.23
(1) (1)
19.50
18.55
0.77
0.73
1998 Nov 10 18
7
L
Ee M
6.48
6.20
0.26
0.24
e
1
3.60
3.05
0.14
0.12
M
E
8.25
7.80
0.32
0.31
EUROPEAN
PROJECTION
10.0
8.3
0.39
0.33
H
0.2542.54 7.62
ISSUE DATE
w
0.010.10 0.30
92-11-17 95-03-11
Z
max.
2.24.2 0.51 3.2
0.0870.17 0.020 0.13
(1)
Page 19
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
SO14: plastic small outline package; 14 leads; body width 3.9 mm
D
c
y
Z
14
pin 1 index
1
e
8
A
2
7
w M
b
p

SOT108-1

E
H
E
A
1
L
detail X
A
X
v M
A
Q
(A )
A
3
θ
L
p
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
mm
inches
A
max.
1.75
0.069
A
1
0.25
0.10
0.010
0.004
A2A
1.45
1.25
0.057
0.049
0.25
0.01
b
3
p
0.49
0.25
0.36
0.19
0.019
0.0100
0.014
0.0075
(1)E(1)
cD
8.75
8.55
0.35
0.34
4.0
3.8
0.16
0.15
1.27
0.050
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT108-1
IEC JEDEC EIAJ
076E06S MS-012AB
REFERENCES
1998 Nov 10 19
eHELLpQZywv θ
1.05
0.041
1.0
0.4
0.039
0.016
0.7
0.25
0.6
0.028
0.01 0.004
0.024
0.25 0.1
0.01
6.2
5.8
0.244
0.228
EUROPEAN
PROJECTION
(1)
0.7
0.3
0.028
0.012
ISSUE DATE
o
8
o
0
95-01-23 97-05-22
Page 20
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
D
c
y
Z 14
pin 1 index
8
A
2
A
E
H
E
1

SOT337-1

A
X
v M
A
Q
(A )
L
p
L
A
3
θ
p
MO-150AB
7
w M
b
p
cD
0.20
6.4
0.09
6.0
REFERENCES
0 2.5 5 mm
scale
(1)E(1)
5.4
0.65 1.25 0.2
5.2
1
e
DIMENSIONS (mm are the original dimensions)
mm
OUTLINE VERSION
SOT337-1
A
max.
2.0
0.21
0.05
1.80
1.65
IEC JEDEC EIAJ
0.25
0.38
0.25
UNIT A1A2A3b
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1998 Nov 10 20
detail X
eHELLpQZywv θ
7.9
7.6
1.03
0.63
0.9
0.7
EUROPEAN
PROJECTION
0.13 0.1
(1)
1.4
0.9
ISSUE DATE
95-02-04 96-01-18
o
8
o
0
Page 21
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
D
c
y
Z
14
pin 1 index
8
17
w M
b
e
p
A
2
A
1
E
H
E
L
detail X

SOT402-1

A
X
v M
A
Q
(A )
3
A
θ
L
p
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A1A2A
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
A
max.
0.15
mm
1.10
OUTLINE VERSION
SOT402-1 MO-153
0.05
0.95
0.80
IEC JEDEC EIAJ
0.25
b
3
p
0.30
0.19
0.2
0.1
(1)E(2) (1)
cD
5.1
4.5
4.3
0.65
4.9
REFERENCES
1998 Nov 10 21
eHELLpQZywv θ
6.6
6.2
0.75
0.50
0.4
0.3
EUROPEAN
PROJECTION
0.13 0.10.21.0
0.72
0.38
ISSUE DATE
94-07-12 95-04-04
o
8
o
0
Page 22
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
SOLDERING Introduction
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011). There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.
Through-hole mount packages
S
OLDERING BY DIPPING OR BY SOLDER WAVE
The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T
stg(max)
). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
M
ANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
Surface mount packages
REFLOW SOLDERING Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C.
W
AVE SOLDERING
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
ANUAL SOLDERING
M Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
1998 Nov 10 22
Page 23
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
Suitability of IC packages for wave, reflow and dipping soldering methods
MOUNTING PACKAGE
WAVE REFLOW
Through-hole mount DBS, DIP, HDIP, SDIP, SIL suitable
(2)
Surface mount HLQFP, HSQFP, HSOP, SMS not suitable
(4)
PLCC
, SO suitable suitable −
LQFP, QFP, TQFP not recommended
(3)
(4)(5)
− suitable suitable −
suitable −
(1)
DIPPING
SQFP not suitable suitable −
SOLDERING METHOD
SSOP, TSSOP, VSO not recommended
(6)
suitable −
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1998 Nov 10 23
Page 24
Philips Semiconductors – a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
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220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381
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Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
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Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415
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Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc.,
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Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381
Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands 245106/00/03/pp24 Date of release: 1998 Nov 10 Document order number: 9397 750 04779
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