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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4024
7-stage binary ripple counter
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
7-stage binary ripple counter 74HC/HCT4024
FEATURES
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4024 are high-speed Si-gate CMOS
devices and are pin compatible with the “4024” of the
The counter advances on the HIGH-to-LOW transition of
CP.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4024 are 7-stage binary ripple counters
with a clock input (
CP), an overriding asynchronous
master reset input (MR) and seven fully buffered parallel
APPLICATIONS
• Frequency dividing circuits
• Time delay circuits
outputs (Q0to Q6).
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
f
max
C
C
I
PD
/ t
PLH
propagation delay CP to Q
0
CL= 15 pF; VCC= 5 V 14 14 ns
maximum clock frequency 90 70 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 25 27 pF
TYPICAL
UNIT
HC HCT
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
December 1990 2
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Philips Semiconductors Product specification
7-stage binary ripple counter 74HC/HCT4024
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
2 MR master reset input (active HIGH)
12, 11, 9, 6, 5, 4, 3 Q
7 GND ground (0 V)
8, 10, 13 n.c. not connected
14 V
CP clock input (HIGH-to-LOW, edge-triggered)
to Q
0
CC
parallel outputs
6
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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Philips Semiconductors Product specification
7-stage binary ripple counter 74HC/HCT4024
FUNCTION TABLE
INPUTS OUTPUTS
Fig.4 Functional diagram.
CP MR Q
↑
↓
X
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock transition
↓=HIGH-to-LOW clock transition
L
L
H
n
no change
count
L
Fig.5 Logic diagram.
December 1990 4
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Philips Semiconductors Product specification
7-stage binary ripple counter 74HC/HCT4024
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
PHL
t
THL
t
W
/ t
/ t
/ t
propagation delay
PLH
CP to Q
0
propagation delay
MR to Q
propagation delay
PLH
Qn to Q
output transition time 19
TLH
0
n+1
clock pulse width
HIGH or LOW
t
W
master reset pulse width
HIGH
t
rem
removal time
MR to CP
f
max
maximum clock pulse
frequency
(°C)
T
amb
74HC
+25 −40 to +125 −40 to +125
min. typ. max. min. max. min. max.
47
80
16
14
80
16
14
50
10
9
6.0
30
35
17
14
63
23
18
25
9
7
7
6
17
6
5
22
8
6
6
2
2
27
82
98
175
35
30
200
40
34
80
16
14
75
15
13
100
20
17
100
20
17
65
13
11
4.8
24
28
220
44
37
250
50
43
100
20
17
95
19
16
265
53
45
300
60
51
120
24
20
110
22
19
120
24
20
120
24
20
75
15
13
4.0
20
24
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
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Philips Semiconductors Product specification
7-stage binary ripple counter 74HC/HCT4024
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
CP
MR
0.75
0.85
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
T
amb
(°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25 −40 to +125 −40 to +125
UNIT
V
(V)
min. typ. max. min. max. min. max.
t
PHL
t
PHL
t
PHL
t
THL
/ t
/ t
/ t
propagation delay
PLH
CP to Q
0
propagation delay
MR to Q
propagation delay
PLH
Qn to Q
output transition time 7 15 19 22 ns 4.5 Fig.6
TLH
0
n+1
17 35 44 53 ns 4.5 Fig.6
21 40 50 60 ns 4.5 Fig.6
9 16 20 24 ns 4.5 Fig.6
WAVEFORMS
CC
t
W
clock pulse width
16 9 20 24 ns 4.5 Fig.6
HIGH or LOW
t
W
master reset pulse width
16 6 20 24 ns 4.5 Fig.6
HIGH
t
rem
removal time
10 0 13 15 ns 4.5 Fig.6
MR to CP
f
max
maximum clock pulse
30 64 24 20 MHz 4.5 Fig.6
frequency
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Philips Semiconductors Product specification
7-stage binary ripple counter 74HC/HCT4024
AC WAVEFORMS
Also showing the master reset (MR) pulse width, the
master reset to output (Q
master reset to clock (
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
) propagation delays and the
n
CP) removal time.
Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
PACKAGE OUTLINES
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
See
.
December 1990 7
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