Datasheet 74 hct4017 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4017

Johnson decade counter with 10 decoded outputs

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product speciﬁcation

Johnson decade counter with 10 decoded outputs 74HC/HCT4017

FEATURES

• Output capability: standard

• ICC category: MSI

CP1) and an overriding asynchronous master reset input (MR).

The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see also function

GENERAL DESCRIPTION

The 74HC/HCT4017 are high-speed Si-gate CMOS devices and are pin compatible with the “4017” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT4017 are 5-stage Johnson decade counters with 10 decoded active HIGH outputs (Q

to Q9),

0

an active LOW output from the most significant flip-flop (Q

), active HIGH and active LOW clock inputs (CP0 and

5-9

table). When cascading counters, the Q

while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter.

A HIGH on MR resets the counter to zero (Q0= Q

= HIGH; Q1 to Q9= LOW) independent of the

5-9

clock inputs (CP0 and CP1). Automatic code correction of the counter is provided by an

internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

/ t

PHL

PLH

f

max

C

I

C

PD

propagation delay CP0, CP1 to Q

n

CL= 15 pF; VCC=5 V2021ns maximum clock frequency 77 67 MHz input capacitance 3.5 3.5 pF power dissipation capacitance per package notes 1 and 2 35 36 pF

output, which is LOW

5-9

TYPICAL

HC HCT

UNIT

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 2

Philips Semiconductors Product speciﬁcation

Johnson decade counter with 10 decoded outputs 74HC/HCT4017

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

3, 2, 4, 7, 10, 1, 5, 6, 9, 11 Q 8 GND ground (0 V) 12 13 14 CP 15 MR master reset input (active HIGH) 16 V

Q CP

to Q

0

5-9

1 0

CC

9

decoded outputs

carry output (active LOW) clock input (HIGH-to-LOW, edge-triggered) clock input (LOW-to-HIGH, edge-triggered)

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product speciﬁcation

Johnson decade counter with 10 decoded outputs 74HC/HCT4017

Fig.4 Functional diagram.

FUNCTION TABLE

MR CP

HXXQ L

L L L L L

H

↑

L X H

↓

CP

0

↓

L X H

↑

L

1

0=Q5-9

counter advances counter advances no change no change no change no change

Notes

1. H = HIGH voltage level L = LOW voltage level X = don’t care

↑ = LOW-to-HIGH clock transition ↓ = HIGH-to-LOW clock transition

OPERATION

= H; Q1 to Q9=L

December 1990 4

Philips Semiconductors Product speciﬁcation

Johnson decade counter with 10 decoded outputs

74HC/HCT4017

Fig.5 Logic diagram.

Fig.6 Timing diagram.

December 1990 5

Philips Semiconductors Product speciﬁcation

Johnson decade counter with 10 decoded outputs 74HC/HCT4017

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see Output capability: standard

ICC category: MSI

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

December 1990 6

Philips Semiconductors Product speciﬁcation

Johnson decade counter with 10 decoded outputs 74HC/HCT4017

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL

/ t

t

PHL

PLH

/ t

t

PHL

PLH

t

/ t

PHL

PLH

/ t

t

PHL

PLH

t

PHL

t

PLH

t

/ t

THL

TLH

t

W

t

W

t

rem

t

su

t

h

f

max

PARAMETER

propagation delay

CP0 to Q

n

propagation delay

CP0 to Q

5-9

propagation delay

CP1 to Q

n

propagation delay

CP1 to Q

5-9

propagation delay

MR to Q

1−9

propagation delay

MR to Q

5−9

, Q

0

output transition time

clock pulse width

HIGH or LOW

master reset pulse

width; HIGH

removal time

MR to CP0, CP

1

set-up time

CP1 to CP0; CP0 to CP

1

hold time

CP0 to CP1; CP1 to CP

0

maximum clock

pulse frequency

(°C)

T

amb

74HC

+25 −40 to+85 −40 to+125

min. typ. max. min. max. min. max.

63

80 16 14

5 5 5

50 10 9

6.0 30 25

23 18

63 23 18

61 22 18

52 19 15

55 20 16

19 7 6

17 6 5

19 7 6

−17

−6

−5

−8

−3

−2

17 6 5

23 70 83

230 46 39

250 50 43

230 46 39

75 15 13

100 20 17

5 5 5

65 13 11

4.8 24 28

290 58 49

315 63 54

290 58 49

95 19 16

345 69 59

375 75 64

345 69 59

110 22 19

120 24 20

5 5 5

75 15 13

4.0 20 24

TEST CONDITIONS

UNIT

V

(V)

ns 2.0

4.5

6.0

ns 2.0

4.5

6.0

ns 2.0

4.5

6.0

ns 2.0

4.5

6.0

ns 2.0

4.5

6.0

ns 2.0

4.5

6.0

ns 2.0

4.5

6.0

ns 2.0

4.5

6.0

ns 2.0

4.5

6.0

ns 2.0

4.5

6.0

ns 2.0

4.5

6.0

ns 2.0

4.5

6.0

MHz 2.0

4.5

6.0

WAVEFORMS

CC

Fig.9

Fig.8

Fig.9

Fig.8

Fig.7

Fig.8

December 1990 7

Philips Semiconductors Product speciﬁcation

Johnson decade counter with 10 decoded outputs 74HC/HCT4017

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: standard ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆I

per input, multiply this value by the unit load coefficient shown in the table below.

CC

INPUT UNIT LOAD COEFFICIENT

CP CP MR

1 0

0.40

0.25

0.50

December 1990 8

Philips Semiconductors Product speciﬁcation

Johnson decade counter with 10 decoded outputs 74HC/HCT4017

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

t

PHL

t

PHL

t

PHL

t

PHL

t

PHL

t

PLH

t

THL

t

W

/ t

PLH

/ t

PLH

/ t

PLH

/ t

PLH

/ t

TLH

propagation delay

CP0 to Q

n

propagation delay

CP0 to Q

5-9

propagation delay

CP1 to Q

n

propagation delay

CP1 to Q

5-9

propagation delay

MR to Q

1−9

propagation delay

MR to Q

5−9

output transition time 7 15 19 22 ns 4.5 Fig.9

clock pulse width

HIGH or LOW

t

W

master reset pulse

width; HIGH

t

rem

removal time

MR to CP0, CP

t

su

set-up time

CP1 to CP0; CP0 to CP

t

h

hold time

1

CP0 to CP1;

f

max

CP1 to CP

maximum clock pulse

0

frequency

, Q

T

amb

(°C)

TEST CONDITIONS

74HCT

+25 −40 to+85 −40 to+125

min. typ. max. min. max. min. max.

UNIT

V

CC

(V)

WAVEFORMS

25 46 58 69 ns 4.5 Fig.9

25 50 63 75 ns 4.5 Fig.9

22 46 58 69 ns 4.5 Fig.8

20 46 58 69 ns 4.5 Fig.8

0

16 7 20 24 ns 4.5 Fig.8

16 4 20 24 ns 4.5 Fig.8

5 −5 5 5 ns 4.5 Fig.8

1

10 −3 13 15 ns 4.5 Fig.7

10 6 13 15 ns 4.5 Fig.7

30 61 24 20 ns 4.5 Fig.8

December 1990 9

Philips Semiconductors Product speciﬁcation

Johnson decade counter with 10 decoded outputs 74HC/HCT4017

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to V

HCT: VM= 1.3 V; VI= GND to 3 V.

.

CC

Fig.7 Waveforms showing the hold and set-up times for CP0 to CP1 and CP1 to CP0.

Conditions: CP1= LOW while CP0 is triggered on a LOW-to-HIGH transition and CP HIGH-to-LOW transition.

(1) HC : V

HCT: VM= 1.3 V; VI= GND to 3 V.

= HIGH, while CP1 is triggered on a

0

= 50%; VI= GND to V

M

CC

.

Fig.8 Waveforms showing the minimum pulse widths for CP0, CP1 and MR inputs; the recovery time for MR and

the propagation delays for MR to Qn and Q

outputs.

5-9

December 1990 10

Philips Semiconductors Product speciﬁcation

Johnson decade counter with 10 decoded outputs 74HC/HCT4017

Conditions: CP1= LOW while CP0 is triggered on a LOW-to-HIGH transition

= HIGH, while CP1 is triggered on a HIGH-to-LOW

and CP

0

transition. (1) HC : V

= 50%; VI= GND to V

M

HCT: VM= 1.3 V; VI= GND to 3 V.

.

CC

Fig.9 Waveforms showing the propagation delays for CP0, CP1 to Qn, Q

outputs and the output transition times.

5-9

December 1990 11

Philips Semiconductors Product speciﬁcation

Johnson decade counter with 10 decoded outputs 74HC/HCT4017

APPLICATION INFORMATION

Some applications for the “4017” are:

• Decade counter with decimal decoding

• 1 out of n decoding counter (when cascaded)

• Sequential controller

• Timer

Figure 10 shows a technique for extending the number of decoded output states for the “4017”. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).

It is essential not to enable the counter on CP when CP0 is HIGH, or on CP0 when CP1 is LOW, as this would cause an extra count.

1

Fig.10 Counter expansion

Figure 11 shows an example of a divide-by 2 through divide-by 10 circuit using one “4017”. Since “4017” has an asynchronous reset, the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output pulse widths can be enlarged by inserting a RC network at the MR input.

Fig.11 Divide-by 2 through divide-by 10.

PACKAGE OUTLINES

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

See

.

December 1990 12