Datasheet 74 hct40102 DATASHEETS (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT40102

8-bit synchronous BCD down counter

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

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Philips Semiconductors Product speciﬁcation

8-bit synchronous BCD down counter 74HC/HCT40102

FEATURES

• Cascadable

• Synchronous or asynchronous preset

• Output capability: standard

• ICCcategory: MSI

GENERAL DESCRIPTION

The 74HC/HCT40102 are high-speed Si-gate CMOS devices and are pin compatible with the “40102” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT40102 consist each of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The “40102” is configured as two cascaded 4-bit BCD counters and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (

TC) are active-LOW logic.

In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero ifTE is LOW, and remains LOW for one full clock period.

When the synchronous preset enable input (PE) is LOW, data at the jam input (P0to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam input (P0to P7) is asynchronously forced into the counter regardless of the state of PE, TE, or CP. The jam inputs (P0to P7) represent two 4-bit BCD words.

When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal

99) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the function table.

If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 clock pulses long. The “40102” may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode.

APPLICATIONS

• Divide-by-n counters

• Programmable timers

• Interrupt timers

• Cycle/program counters

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

PHL

max

C C

I PD

/ t

PLH

propagation delay CP to TC CL= 15 pF; VCC= 5 V 30 31 ns maximum clock frequency 30 30 MHz input capacitance 3.5 3.5 pF power dissipation capacitance per package notes 1 and 2 20 25 pF

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD=CPD× V

× fi+∑(CL× V

× fo) where:

fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

× fo) = sum of outputs

CL= output load capacitance in pF VCC= supply voltage in V

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TYPICAL

UNIT

HC HCT

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Philips Semiconductors Product speciﬁcation

8-bit synchronous BCD down counter 74HC/HCT40102

2. For HC the condition is VI= GND to V

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 CP clock input (LOW-to-HIGH, edge-triggered) 2 3 4, 5, 6, 7, 10, 11, 12, 13 P

MR asynchronous master reset input (active LOW) TE terminal enable input

to P

jam inputs 8 GND ground (0 V) 9 14 15 16 V

PL asynchronous preset enable input (active LOW) TC terminal count output (active LOW) PE synchronous preset enable input (active LOW)

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

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Philips Semiconductors Product speciﬁcation

8-bit synchronous BCD down counter 74HC/HCT40102

Fig.4 Functional diagram.

FUNCTION TABLE

CONTROL INPUTS

MR PL PE TE

HHHH H H H L count down H H L X preset on next LOW-to HIGH clock transition HLXX

L X X X clear to maximum count

Notes

1. Clock connected to CP.

2. Synchronous operation: changes occur on the LOW-to-HIGH CP transition.

3. Jam inputs: MSD = P

H = HIGH voltage level L = LOW voltage level X = don’t care

, LSD = P0.

PRESET MODE ACTION

inhibit counter

synchronous

asynchronous

preset asynchronously

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Philips Semiconductors Product speciﬁcation

8-bit synchronous BCD down counter 74HC/HCT40102

Fig.5 Logic diagram.

Fig.6 Timing diagram.

December 1990 5

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Philips Semiconductors Product speciﬁcation

8-bit synchronous BCD down counter 74HC/HCT40102

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard ICCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

PHL

/ t

propagation delay

PLH

CP to TC

PHL

/ t

propagation delay

PLH

TE to TC

PHL

/ t

propagation delay

PLH

Pn, PL to TC

PLH

propagation delay

MR to TC

THL

/ t

output transition time 9

TLH

clock pulse width

HIGH or LOW

master reset pulse width

LOW

preset enable pulse width

PL; LOW

rem

removal time

PL; MR to CP

set-up time

PE to CP

set-up time

TE to CP

(°C)

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

165 33 28

150 30 26

125 25 21

50 10 9

100 20 17

175 35 30

35 28

50 18 14

110 40 32

83 30 24

7 6

22 8 6

30 11 9

39 14 11

8 3 2

36 13 10

50 18 14

300 60 51

200 40 34

240 68 58

275 55 47

75 15 13

205 41 35

190 38 33

155 31 26

65 13 11

125 25 21

220 44 37

375 75 64

250 50 43

425 85 72

345 69 59

95 19 16

450 90 77

300 60 51

510 102 87

415 83 71

110 22 19

250 50 43

225 45 38

190 38 32

75 15 13

150 30 26

265 53 45

UNIT

ns 2.0

TEST CONDITIONS

WAVEFORMS

(V)

Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0 Figs 8 and 8

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0

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Philips Semiconductors Product speciﬁcation

8-bit synchronous BCD down counter 74HC/HCT40102

SYMBOL PARAMETER

set-up time

Pnto CP

hold time

PE to CP

hold time

TE to CP

hold time

Pnto CP

max

maximum clock pulse

frequency

(°C)

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

100 20 17

2 2 2

0 0 0

2 2 2

3 15 18

33 12 10

−8

−3

−2

−41

−15

−12

−5

8.9 27 32

125 25 21

2 2 2

0 0 0

2 2 2

2 12 14

150 30 26

2 2 2

0 0 0

2 2 2

2 10 12

UNIT

ns 2.0

MHz 2.0

TEST CONDITIONS

WAVEFORMS

(V)

Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0

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Philips Semiconductors Product speciﬁcation

8-bit synchronous BCD down counter 74HC/HCT40102

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see Output capability: standard

ICCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆I

INPUT UNIT LOAD COEFFICIENT

CP, MR TE P

per input, multiply this value by the unit load coefficient shown in the table below.

1.50

1.00

0.80

0.25

0.35

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

December 1990 8

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Philips Semiconductors Product speciﬁcation

8-bit synchronous BCD down counter 74HC/HCT40102

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

PHL

/ t

propagation delay

PLH

Pn; CP to TC

PHL

/ t

propagation delay

PLH

TE to TC

PHL

/ t

propagation delay

PLH

PL to TC

PLH

propagation delay

MR to TC

THL

/ t

output transition time 7 15 19 22 ns 4.5 Figs 8 and 8

TLH

clock pulse width

HIGH or LOW

master reset pulse width

LOW

preset enable pulse width

PL; LOW

rem

removal time

PL; MR to CP

set-up time

PE to CP

set-up time

TE to CP

set-up time

Pnto CP

hold time

PE to CP

hold time

TE to CP

hold time

Pnto CP

max

maximum clock pulse

frequency

amb

(°C)

TEST CONDITIONS

74HCT

+25 −40 to +85 −40 to +125

UNIT

WAVEFORMS

(V)

min. typ. max. min. max. min. max.

38 63 79 95 ns 4.5 Figs 8 and 8

25 50 63 75 ns 4.5 Fig.8

49 83 104 125 ns 4.5 Fig.8

31 55 69 83 ns 4.5 Fig.8

33 11 41 50 ns 4.5 Fig.8

30 16 38 45 ns 4.5 Fig.8

43 25 54 65 ns 4.5 Fig.8

10 1 13 15 ns 4.5 Fig.8

20 10 25 30 ns 4.5 Fig.8

40 20 50 60 ns 4.5 Fig.8

20 12 25 30 ns 4.5 Fig.8

0 −4 0 0 ns 4.5 Fig.8

0 −15 0 0 ns 4.5 Fig.8

0 −6 0 0 ns 4.5 Fig.8

15 27 12 10 MHz 4.5 Fig.8

December 1990 9

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Philips Semiconductors Product speciﬁcation

8-bit synchronous BCD down counter 74HC/HCT40102

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3 V; VI= GND to 3 V.

Fig.7 Waveforms showing the clock input (CP) to

TC propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3 V; VI= GND to 3 V.

Fig.9 Waveforms showingPL, MR, Pnto

TC propagation delays.

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

Fig.8 Waveforms showing theTE to

TC propagation delays.

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

Fig.10 Waveforms showing removal time for

MR and PL.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3 V; VI= GND to 3 V.

Fig.11 Waveforms showing hold and set-up times

for MR or PE to CP.

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The shaded areas indicate when the input is permitted to change for predictable output performance.

(1) HC : V

HCT: V

= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

Fig.12 Waveforms showing hold and set-up times

for Pn, PE to CP.

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Philips Semiconductors Product speciﬁcation

8-bit synchronous BCD down counter 74HC/HCT40102

APPLICATION INFORMATION

PACKAGE OUTLINES

Fig.13 Programmable timer.

Fig.14 Divide-by-N counter.

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

December 1990 11