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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT377
Octal D-type flip-flop with data
enable; positive-edge trigger
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
FEATURES
• Ideal for addressable register applications
• Data enable for address and data synchronization
applications
• Eight positive-edge triggered D-type flip-flops
• See “273” for master reset version
• See “373” for transparent latch version
• See “374” for 3-state version
• Output capability: standard
• ICC category: MSI
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
f
max
C
C
I
PD
/ t
PLH
propagation delay CP to Q
n
maximum clock frequency 77 53 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per flip-flop notes 1 and 2 20 20 pF
GENERAL DESCRIPTION
The 74HC/HCT377 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT377 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. A common
clock (CP) input loads all flip-flops simultaneously when
the data enable (E) is LOW. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the flip-flop.
TheE input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
CL= 15 pF; VCC= 5 V 13 14 ns
74HC/HCT377
TYPICAL
UNIT
HC HCT
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
December 1990 2
Page 3
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
74HC/HCT377
positive-edge trigger
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
2, 5, 6, 9, 12, 15, 16, 19 Q
3, 4, 7, 8, 13, 14, 17, 18 D
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge-triggered)
20 V
E data enable input (active LOW)
to Q
0
to D
0
CC
7
7
flip-flop outputs
data inputs
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
Page 4
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74HC/HCT377
FUNCTION TABLE
OPERATING
MODES
load “1” ↑ lh H
load “0” ↑ ll L
hold (do nothing) ↑
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time
prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time
prior to the LOW-to-HIGH CP transition
↑ = LOW-to-HIGH CP transition
X = don’t care
INPUTS OUTPUTS
CP ED
h
X
H
n
X
X
no change
no change
Q
n
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990 4
Page 5
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
SYMBOL PARAMETER
t
PHL
t
THL
t
W
/ t
/ t
propagation delay
PLH
CP to Q
output transition time 19
TLH
n
clock pulse width
HIGH or LOW
t
su
set-up time
Dn to CP
t
su
set-up time
E to CP
t
h
hold time
Dn to CP
t
h
hold time
E to CP
f
max
maximum clock pulse
frequency
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
44
16
13
7
6
80
14
16
5
14
4
60
14
12
5
10
4
60
6
12
2
10
2
3
−8
3
−3
3
−2
4
−3
4
−1
4
−1
6
23
30
70
35
83
160
32
27
75
15
13
T
amb
74HC
100
20
17
75
15
13
75
15
13
3
3
3
4
4
4
5
24
28
(°C)
200
40
34
95
19
16
120
24
20
90
18
15
90
18
15
3
3
3
4
4
4
4
20
24
240
48
41
110
22
19
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
74HC/HCT377
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.6
4.5
6.0
December 1990 5
Page 6
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
74HC/HCT377
positive-edge trigger
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
E
CP
D
n
1.50
0.50
0.20
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
) for a unit load of 1 is given in the family specifications.
CC
.
SYMBOL PARAMETER
t
PHL
t
THL
t
W
/ t
/ t
propagation delay
PLH
CP to Q
output transition time 7 15 19 22 ns 4.5 Fig.6
TLH
n
clock pulse width
HIGH or LOW
t
su
set-up time
Dn to CP
t
su
set-up time
E to CP
t
h
hold time
Dn to CP
t
h
hold time
E to CP
f
max
maximum clock pulse
frequency
T
amb
(°C)
TEST CONDITIONS
74HCT
+25 −40 to +85 −40 to +125
UNIT
WAVEFORMS
V
CC
(V)
min. typ. max. min. max. min. max.
17 32 40 48 ns 4.5 Fig.6
20 8 25 30 ns 4.5 Fig.6
12 4 15 18 ns 4.5 Fig.7
22 12 28 33 ns 4.5 Fig.7
2 −4 2 2 ns 4.5 Fig.7
3 −2 3 3 ns 4.5 Fig.7
27 48 22 18 MHz 4.5 Fig.6
December 1990 6
Page 7
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
74HC/HCT377
positive-edge trigger
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output
= 1.3 V; VI= GND to 3 V.
M
transition times and the maximum clock pulse frequency.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
HCT : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
Fig.7 Waveforms showing the data set-up and hold times from the data input (Dn) and from the data enable input
(E) to the clock (CP).
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 7
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