Datasheet 74 hct374 DATASHEETS (Philips)

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Page 1

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT374

Octal D-type flip-flop; positive edge-trigger; 3-state

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

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Philips Semiconductors Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

FEATURES

• 3-state non-inverting outputs for bus oriented applications

• 8-bit positive, edge-triggered register

• Common 3-state output enable input

• Independent register and 3-state buffer operation

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

74HC/HCT374

The 74HC/HCT374 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (

The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition.

When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

The “374” is functionally identical to the “534”, but has non-inverting outputs.

OE) input are common to all flip-flops.

SYMBOL PARAMETER CONDITIONS

PHL

max

C C

I PD

/ t

PLH

propagation delay CP to Q

CL= 15 pF; VCC= 5 V 15 13 ns maximum clock frequency 77 48 MHz input capacitance 3.5 3.5 pF power dissipation capacitance per ﬂip-ﬂop notes 1 and 2 17 17 pF

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

× fi+∑ (CL× V

× fo) where:

fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

× fo) = sum of outputs

CL= output load capacitance in pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

TYPICAL

UNIT

HC HCT

December 1990 2

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Philips Semiconductors Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger;

74HC/HCT374

3-state

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 2, 5, 6, 9, 12, 15, 16, 19 Q 3, 4, 7, 8, 13, 14, 17, 18 D 10 GND ground (0 V) 11 CP clock input (LOW-to-HIGH, edge-triggered) 20 V

OE 3-state output enable input (active LOW)

to Q

to D

3-state ﬂip-ﬂop outputs data inputs

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

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Philips Semiconductors Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

FUNCTION TABLE

OPERATING

MODES

load and read register

load register and disable outputs

Notes

1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH

CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP

transition Z = high impedance OFF-state ↑ = LOW-to-HIGH CP transition

INPUTS

OE CP D

LL↑

↑lh

HH↑

↑lh

INTERNAL

FLIP-FLOPS

74HC/HCT374

OUTPUTS

Q0to Q

L H

H Z

Fig.4 Functional diagram.

Fig.5 Logic diagram.

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Philips Semiconductors Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see Output capability: bus driver

ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL=50pF

r=tf

SYMBOL PARAMETER

PHL

PZH

PHZ

THL

/ t

propagation delay

PLH

CP to Q

3-state output enable time

PZL

OE to Q

3-state output disable time

PLZ

OE to Q

output transition time 14

TLH

clock pulse width

HIGH or LOW

set-up time

Dn to CP

hold time

Dn to CP

max

maximum clock pulse

frequency

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

165

150

26 60

−6

−2

6.0

amb

74HC

100 20 17

75 15 13

5 5 5

4.8 24 28

(°C)

205 41 35

190 38 33

75 15 13

120 24 20

90 18 15

5 5 5

4.0 20 24

250 50 43

225 45 38

90 18 15

UNIT

ns 2.0

MHz 2.0

74HC/HCT374

TEST CONDITIONS

WAVEFORMS

(V)

Fig.6

4.5

6.0 Fig.7

4.5

6.0 Fig.7

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.6

4.5

6.0

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Philips Semiconductors Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger;

74HC/HCT374

3-state

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see Output capability: bus driver

ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

OE CP D

1.25

0.90

0.35

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL=50pF

r=tf

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

) for a unit load of 1 is given in the family specifications.

SYMBOL PARAMETER

PHL

PZH

PHZ

THL

/ t

propagation delay

PLH

CP to Q

3-state output enable time

PZL

OE to Q

3-state output disable time

PLZ

OE to Q

output transition time 5 12 15 18 ns 4.5 Fig.6

TLH

clock pulse width

HIGH or LOW

set-up time

Dn to CP

hold time

Dn to CP

max

maximum clock pulse

frequency

amb

(°C)

TEST CONDITIONS

74HCT

+25 −40 to +85 −40 to +125

UNIT

WAVEFORMS

(V)

min. typ. max. min. max. min. max.

16 32 40 48 ns 4.5 Fig.6

16 30 38 45 ns 4.5 Fig.7

18 28 35 42 ns 4.5 Fig.7

19 11 24 29 ns 4.5 Fig.6

12 7 15 18 ns 4.5 Fig.8

5 −3 5 5 ns 4.5 Fig.8

26 44 21 17 MHz 4.5 Fig.6

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Philips Semiconductors Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger;

74HC/HCT374

3-state

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

HCT : V

Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output

= 1.3 V; VI= GND to 3 V.

transition times and the maximum clock pulse frequency.

(1) HC : VM= 50%; VI= GND to VCC.

HCT : V

= 1.3 V; VI= GND to 3 V.

Fig.7 Waveforms showing the 3-state enable and disable times.

The shaded areas indicate when the input is permitted to change for predictable output performance.

(1) HC : V

HCT : V

= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

Fig.8 Waveforms showing the data set-up and hold times for Dn input.

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Philips Semiconductors Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

74HC/HCT374

December 1990 8