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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT368
Hex buffer/line driver; 3-state;
inverting
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Hex buffer/line driver; 3-state; inverting 74HC/HCT368
FEATURES
• Inverting outputs
• Output capability: bus driver
• ICC category: MSI
The 74HC/HCT368 are hex inverting buffer/line drivers
with 3-state outputs. The 3-state outputs (n
controlled by the output enable inputs (1OE, 2OE).
A HIGH on nOE causes the outputs to assume a high
impedance OFF-state.
The “368” is identical to the “367” but has inverting outputs.
GENERAL DESCRIPTION
The 74HC/HCT368 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
C
C
I
PD
/ t
PLH
propagation delay nA to nYC
= 15 pF; VCC=5V 9 11 ns
L
input capacitance 3.5 3.5 pF
power dissipation capacitance per buffer notes 1 and 2 30 30 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC−1.5 V
Y) are
TYPICAL
UNIT
HC HCT
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
December 1990 2
.
Page 3
Philips Semiconductors Product specification
Hex buffer/line driver; 3-state; inverting 74HC/HCT368
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 15 1
2, 4, 6, 10, 12, 14 1A to 6A data inputs
3, 5, 7, 9, 11, 13 1
8 GND ground (0 V)
16 V
OE, 2OE output enable inputs (active LOW)
Y to 6Y data outputs
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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Philips Semiconductors Product specification
Hex buffer/line driver; 3-state; inverting 74HC/HCT368
FUNCTION TABLE
INPUTS OUTPUTS
OE nA nY
n
L
L
H
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
L
H
X
H
L
Z
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990 4
Page 5
Philips Semiconductors Product specification
Hex buffer/line driver; 3-state; inverting 74HC/HCT368
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
SYMBOL PARAMETER
t
PHL
/ t
propagation delay
PLH
nA to nY
t
PZH
/ t
3-state output enable time
PZL
nOE to nY
t
PHZ
/ t
3-state output disable time
PLZ
nOE to nY
t
THL
/ t
output transition time 14
TLH
(°C)
T
amb
74HC
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
30
11
9
41
15
12
55
20
16
5
4
95
19
16
150
30
26
150
30
26
60
12
10
120
24
20
190
38
33
190
38
33
75
15
13
145
29
25
225
45
38
225
45
38
90
18
15
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.6
4.5
6.0
December 1990 5
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Philips Semiconductors Product specification
Hex buffer/line driver; 3-state; inverting 74HC/HCT368
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
1OE
2OE
nA
1.00
0.90
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
T
amb
(°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25 −40 to +85 −40 to +125
UNIT
V
(V)
min. typ. max. min. max. min. max.
t
PHL
/ t
propagation delay
PLH
13 24 30 36 ns 4.5 Fig.6
nA to nY
t
PZH
/ t
3-state output enable time
PZL
17 35 44 53 ns 4.5 Fig.7
nOE to nY
t
PHZ
/ t
3-state output disable time
PLZ
20 35 44 53 ns 4.5 Fig.7
nOE to nY
t
THL
/ t
output transition time 5 12 15 18 ns 4.5 Fig.6
TLH
WAVEFORMS
CC
December 1990 6
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Philips Semiconductors Product specification
Hex buffer/line driver; 3-state; inverting 74HC/HCT368
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.6 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.7 Waveforms showing the 3-state enable and disable times.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 7
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