Datasheet 74 hct356 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT356

8-input multiplexer/register; 3-state

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

FEATURES

• Non-transparent data latches

• Transparent address latch

• Easily expanding

• Complementary outputs

• Output capability: bus driver

• ICC category: MSI

(LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT356 data selectors/multiplexers contain full on-chip binary decoding, to select one-of-eight data sources. The data select address is stored in transparent latches that are enabled by a LOW on the latch enable input

LE.

Data on the 8 input lines (D0 to D7) is clocked into a edge-triggered data register by a LOW-to-HIGH transition

GENERAL DESCRIPTION

The 74HC/HCT356 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL

of the clock (CP). When the output enable input OE1= HIGH, OE2= HIGH or OE3= LOW, the outputs go to the high impedance OFF-state. Operation of these output enable inputs does not affect the state of the latches and register.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL/ tPLH

C

I

C

PD

propagation delay CL= 15 pF; VCC=5 V

,LE to Y, Y2425ns

S

n

CP to Y,

Y2022ns input capacitance 3.5 3.5 pF power dissipation capacitance per package notes 1 and 2 123 125 pF

TYPICAL

UNIT

HC HCT

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 2

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

8, 7, 6, 5, 4, 3, 2, 1 D 9 CP clock input data (LOW-to-HIGH, edge-triggered) 10 GND ground (0 V) 11 14, 13, 12 S 15, 16 17 OE 18 19 Y 3-state multiplexer output (active HIGH) 20 V

to D

0

7

data inputs

LE address latch enable input (active LOW)

, S1, S

0

OE1, OE

3

2

select inputs output enable inputs (active LOW) output enable input (active HIGH)

Y 3-state multiplexer output (active LOW)

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

FUNCTION TABLE

INPUTS OUTPUTS

(1)

OUTPUT ENABLE

DESCRIPTIONADDRESS

2

X X X

L L L L

H H H H

L L L L

H H H H

S

1

X X X

L L H H

X X X

L H L H

CP

S

0

X X X

↑ ↑ ↑ ↑

(2) (2) (2) (2)

OE

1

H X X

L L L L

OE

2

X H X

L L L L

OE

X X L

H H H H

Y YS

3

Z Z Z

D

0n

D

1n

D

2n

D

3n

D

4n

D

5n

D

6n

D

7n

D

0p

D

1p

D

2p

D

3p

D

4p

D

5p

D

6p

D

7p

Z Z Z

D

0n

D

1n

D

2n

D

3n

D

4n

D

5n

D

6n

D

7n

D

0p

D

1p

D

2p

D

3p

D

4p

D

5p

D

6p

D

7p

outputs in high impedance OFF-state

data is clocked into latch

outputs do not change states

Notes

1. This column shows the input address set-up with

LE = LOW (address latch is transparent).

2. CP is HIGH, LOW or ↓.

3. D0n to D7n= data present at inputs D0 to D7 when the data latch clock made the transition from LOW-to-HIGH D0p to D7p= data previously latched into the data latch by the LOW-to-HIGH transition of the data latch clock H = HIGH voltage level L = LOW voltage level X = don’t care

↑ = LOW-to-HIGH CP transition ↓ = HIGH-to-LOW CP transition

Z = high impedance OFF-state

December 1990 4

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

Fig.4 Functional diagram.

December 1990 5

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

Fig.5 Logic diagram.

December 1990 6

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: bus driver ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

SYMBOL PARAMETER

/ t

t

PHL

PLH

= 6 ns; CL= 50 pF

r=tf

propagation delay

CP to Y, Y

t

/ t

PHL

propagation delay

PLH

Sn to Y, Y

t

/ t

PHL

propagation delay

PLH

LE to Y, Y

t

/ t

PZH

3-state output enable time

PZL

OEn to Y, Y

t

/ t

PZH

3-state output enable time

PZL

OE3 to Y, Y

/ t

t

PHZ

3-state output disable time

PLZ

OEn to Y, Y

t

/ t

PHZ

3-state output disable time

PLZ

OE3 to Y, Y

t

/ t

THL

t

W

output transition time 14

TLH

clock pulse width CP

HIGH or LOW

t

W

latch enable pulse width LE

LOW

t

su

set-up time

Dn to CP

T

(°C)

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

66

80 16 14

50 10 9

24 19

77 28 22

41 15 12

47 17 14

50 18 14

58 21 17

5 4

17 6 5

11 4 3

240 48 41

260 52 44

270 54 46

125 25 21

150 30 26

155 31 26

60 12 10

100 20 17

65 13 11

300 60 51

325 65 55

340 68 58

155 31 26

190 38 33

195 39 33

75 15 13

360 72 61

390 78 66

405 81 69

190 38 32

225 45 38

235 47 40

90 18 15

120 24 20

75 15 13

.

UNIT

ns 2.0

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.6

4.5

6.0 Fig.7

4.5

6.0 Fig.8

4.5

6.0 Fig.11

4.5

6.0 Fig.11

4.5

6.0 Fig.11

4.5

6.0 Fig.11

4.5

6.0 Figs 6, 7 and 8

4.5

6.0 Fig.6

4.5

6.0 Fig.8

4.5

6.0 Fig.10

4.5

6.0

December 1990 7

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

T

SYMBOL PARAMETER

t

su

set-up time

Sn to LE

t

h

hold time

Dn to CP

t

h

hold time

Sn to LE

(°C)

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

50 10 9

5 5 5

14 5 4

−6

−2

−8

−3

−2

65 13 11

5 5 5

75 15 13

5 5 5

UNIT

ns 2.0

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.9

4.5

6.0 Fig.10

4.5

6.0 Fig.9

4.5

6.0

December 1990 8

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: bus driver ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I

) for a unit load of 1 is given in the family specifications.

CC

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

Dn, S

n

OE

3

LE OEn, CP

0.2

0.25

0.5

1.0

December 1990 9

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

t

PHL

/ t

propagation delay

PLH

CP to Y, Y

t

PHL

/ t

propagation delay

PLH

Sn to Y, Y

t

PHL

/ t

propagation delay

PLH

LE to Y, Y

t

PZH

/ t

3-state output enable time

PZL

OEn to Y, Y

t

PZH

/ t

3-state output enable time

PZL

OE3 to Y, Y

t

PHZ

/ t

3-state output disable time

PLZ

OEn to Y, Y

t

PHZ

/ t

3-state output disable time

PLZ

OE3 to Y, Y

t

THL

t

W

/ t

output transition time 5 12 15 18 ns 4.5 Figs 6, 7 and 8

TLH

clock pulse width CP

HIGH or LOW

t

W

latch enable pulse width

LE LOW

t

su

set-up time

Dn to CP

t

su

set-up time

Sn to LE

t

h

hold time

Dn to CP

t

h

hold time

Sn to LE

T

amb

(°C)

TEST CONDITIONS

74HCT

+25 −40 to +85 −40 to +125

UNIT

WAVEFORMS

V

CC

(V)

min. typ. max. min. max. min. max.

26 51 64 77 ns 4.5 Fig.6

28 59 74 89 ns 4.5 Fig.7

29 63 79 95 ns 4.5 Fig.8

17 34 43 51 ns 4.5 Fig.11

18 34 43 51 ns 4.5 Fig.11

17 33 41 50 ns 4.5 Fig.11

20 33 41 50 ns 4.5 Fig.11

16 8 20 24 ns 4.5 Fig.6

16 6 20 24 ns 4.5 Fig.8

10 4 13 15 ns 4.5 Fig.10

10 5 13 15 ns 4.5 Fig.9

5 0 5 5 ns 4.5 Fig.10

5 −2 5 5 ns 4.5 Fig.9

December 1990 10

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.6 Waveforms showing the clock (CP) to the output (Y,Y) propagation delays, the clock pulse width and the

output transition times.

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.7 Waveforms showing the select input (Sn) to output (Y, Y) propagation delays and the output transition

times (LE = LOW).

December 1990 11

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.8 Waveforms showing the address latch enable input (LE) pulse width, the latch enable input to output

(Y, Y) propagation delays and the output transition times.

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.9 Waveforms showing the set-up and hold times for the select input (Sn) to the address latch enable input

(LE).

December 1990 12

Philips Semiconductors Product speciﬁcation

8-input multiplexer/register; 3-state 74HC/HCT356

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.10 Waveforms showing the set-up and hold times for the data input (Dn) to the clock (CP).

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.11 Waveforms showing the 3-state enable and disable times.

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.

December 1990 13