
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT30
8-input NAND gate
Product specification
File under Integrated Circuits, IC06
December 1990

Philips Semiconductors Product specification
8-input NAND gate 74HC/HCT30
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT30 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT30 provide the 8-input NAND function.
QUICK REFERENEC DATA
GND = 0 V; T
=25°C; tr=tf=6ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
C
C
I
PD
/ t
PLH
propagation delay A, B, C, D, E, F, G, H to Y CL= 15 pF; VCC= 5 V 12 12 ns
input capacitance 3.5 3.5 pF
power dissipation capacitance per gate notes 1 and 2 15 15 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
TYPICAL
UNIT
HC HCT
December 1990 2

Philips Semiconductors Product specification
8-input NAND gate 74HC/HCT30
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1 A data input
2 B data input
3 C data input
4 D data input
5 E data input
6 F data input
7 GND ground (0 V)
8 Y data output
9, 10, 13 n.c. not connected
11 G data input
12 H data input
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3

Philips Semiconductors Product specification
8-input NAND gate 74HC/HCT30
Fig.4 Functional diagram;
Y=ABCDEFGH.
FUNCTION TABLE
INPUTS OUTPUT
ABCDEFGH Y
L
X
X
X
X
X
X
X
HHHHHHHH L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
Fig.5 Logic diagram.
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
December 1990 4

Philips Semiconductors Product specification
8-input NAND gate 74HC/HCT30
DC CHARACTERISTICS FOR 74 HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=tf= 6 ns; CL=50pF
SYMBOL PARAMETER
t
PHL
/ t
propagation delay
PLH
A, B, C, D, E, F, G, H to Y
t
THL
/ t
output transition time 19
TLH
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
T
(°C)
amb
74HC
min. typ. max. min. max. min. max.
41
15
12
7
6
130
26
22
75
15
13
165
33
28
95
19
16
195
39
33
110
22
19
.
UNIT
ns 2.0
ns 2.0
.
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to + 85 −40 to +125
(V)
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Output capability: standard
ICC category: SSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆I
per input, multiply this value by the unit load coefficient shown in the table below.
CC
INPUT UNIT LOAD COEFFICIENT
A, B, C, D, E, F, G, H 0.60
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
T
amb
(°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
−40
to +125
UNIT
V
CC
(V)
WAVEFORMS+25 −40 to + 85
min. typ. max. min. max. min. max.
t
PHL
/ t
propagation delay
PLH
16 28 35 42 ns 4.5 Fig.6
A, B, C, D, E, F, G, H to Y
t
THL
/ t
output transition time 7 15 19 22 ns 4.5 Fig.6
TLH
December 1990 5

Philips Semiconductors Product specification
8-input NAND gate 74HC/HCT30
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to V
HCT: VM= 1.3 V; VI= GND to 3 V.
CC.
Fig.6 Waveforms showing the input (A, B, C, D, E, F, G, H) to output (Y) propagation delays and the output
transition times.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 6