Datasheet 74 hct299 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT299

8-bit universal shift register; 3-state

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product speciﬁcation

8-bit universal shift register; 3-state 74HC/HCT299

FEATURES

• Multiplexed inputs/outputs provide improved bit density

• Four operating modes:

– shift left – shift right – hold (store) – load data

• Operates with output enable or at high-impedance OFF-state (Z)

• 3-state outputs drive bus lines directly

• Can be cascaded for n-bits word length

• Output capability: bus driver (parallel I/Os),

standard (serial outputs)

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT299 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT299 contain eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. The type of operation is determined by the mode select inputs (S

and S1), as shown in the mode

0

select table. All flip-flop outputs have 3-state buffers to separate these outputs (I/O0 to I/O7) such, that they can serve as data inputs in the parallel load mode. The serial outputs (Q0 and Q7) are used for expansion in serial shifting of longer words.

A LOW signal on the asynchronous master reset input (MR) overrides the Sn and clock (CP) inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock pulse. Inputs can change when the clock is either state, provided that the recommended set-up and hold times, relative to the rising edge of CP, are observed.

A HIGH signal on the 3-state output enable inputs (OE1 or OE2) disables the 3-state buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition, the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1, when in preparation for a parallel load operation.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL/ tPLH

t

PHL

f

max

C

I

C

I/O

C

PD

propagation delay CL= 15 pF; VCC=5 V

CP to Q CP to I/O MR to Q0, Q7 or I/O

0

, Q

n

7

n

maximum clock frequency 50 46 MHz input capacitance 3.5 3.5 pF input/output capacitance 10 10 pF power dissipation capacitance per package notes 1 and 2 120 125 pF

Notes

1. CPD is used to determine the dynamic power

dissipation (PD in µW):

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

2

× fo) = sum of outputs

CC

2. For HC the condition is V For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package

See

Information”

. CL= output load capacitance in pF VCC= supply voltage in V

TYPICAL

HC HCT

20 19 ns 20 19 ns 20 23 ns

= GND to V

I

CC

UNIT

December 1990 2

Philips Semiconductors Product speciﬁcation

8-bit universal shift register; 3-state 74HC/HCT299

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 19 S 2, 3 7, 13, 6, 14, 5, 15, 4, 16 I/O 8, 17 Q 9 10 GND ground (0 V) 11 D 12 CP clock input (LOW-to-HIGH, edge-triggered) 18 D 20 V

, S

0

1

OE1, OE

to I/O

0

, Q

0

7

2

mode select inputs 3-state output enable inputs (active LOW) parallel data inputs or 3-state parallel outputs (bus driver)

7

serial outputs (standard output)

MR asynchronous master reset input (active LOW)

SR

SL CC

serial data shift-right input

serial data shift-left input positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product speciﬁcation

8-bit universal shift register; 3-state 74HC/HCT299

Fig.4 Functional diagram.

MODE SELECT TABLE

INPUTS

MR S

1

S

0

CP

L X X X asynchronous reset; Q H

H H H

H L H L

H H L L

↑ ↑ ↑

X

parallel load; I/O

n

→ Q shift right; DSR→ Q0, Q0 → Q1 etc. shift left; DSL→ Q7, Q7→ Q6 etc. hold

Notes

1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH CP transition

0−Q7 n

RESPONSE

= LOW

December 1990 4

Philips Semiconductors Product speciﬁcation

8-bit universal shift register; 3-state 74HC/HCT299

Fig.5 Logic diagram.

December 1990 5

Philips Semiconductors Product speciﬁcation

8-bit universal shift register; 3-state 74HC/HCT299

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: bus driver (parallel I/Os)

standard (serial outputs)

ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr=tf= 6 ns; CL= 50 pF

SYMBOL PARAMETER

/ t

t

PHL

t

PHL

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

THL

propagation delay

PLH

CP to Q0, Q

/ t

propagation delay

PLH

CP to I/O

7

n

/ propagation delay

MR to Q0, Q7 or I/O

3-state output enable time

OEn to I/O

n

3-state output enable time

OEn to I/O

n

3-state output disable time

OEn to I/O

n

3-state output disable time

OEn to I/O

/ t

output transition time

TLH

n

bus driver (I/On)

t

/ t

THL

output transition time

TLH

standard (Q0, Q7)

t

W

clock pulse width

HIGH or LOW

t

W

master reset pulse width

LOW

T

(°C)

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

66

80 16 14

24 19

66 24 19

50 18 14

41 15 12

66 24 19

55 20 16

14 5 4

19 7 6

17 6 5

19 7 6

200 40 34

155 31 26

130 26 22

185 37 31

155 31 26

60 12 10

75 15 13

100 20 17

250 50 43

195 39 33

165 33 28

230 46 39

195 39 33

75 15 13

95 19 16

300 60 51

235 47 40

195 39 33

280 56 48

235 47 40

90 18 15

110 22 19

120 24 20

.

UNIT

ns 2.0

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.7

4.5

6.0 Fig.9

4.5

6.0 Fig.9

4.5

6.0 Fig.9

4.5

6.0 Fig.9

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.7

4.5

6.0

December 1990 6

Philips Semiconductors Product speciﬁcation

8-bit universal shift register; 3-state 74HC/HCT299

T

SYMBOL PARAMETER

t

rem

removal time

MR to CP

t

su

set-up time

DSR, DSLto CP

t

su

set-up time

S0, S1to CP

t

su

set-up time

I/On to CP

t

h

hold time

I/On, DSR, DSL to CP

t

h

hold time

S0, S1 to CP

f

max

maximum clock pulse

frequency

(°C)

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

5 5 5

100 20 17

125 25 21

0 0 0

5.0 25 29

−14

−5

−4

33 12 10

39 14 11

−14

−5

−4

−28

−10

−8

15 45 54

5 5 5

125 25 21

155 31 26

0 0 0

4.0 20 24

5 5 5

150 30 26

190 38 32

0 0 0

3.4 17 20

UNIT

ns 2.0

MHz 2.0

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.7

4.5

6.0 Fig.6

4.5

6.0 Fig.8

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.8

4.5

6.0 Fig.6

4.5

6.0

December 1990 7

Philips Semiconductors Product speciﬁcation

8-bit universal shift register; 3-state 74HC/HCT299

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: bus driver (parallel I/Os)

standard (serial outputs)

ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I

) for unit load of 1 is given in the family specifications.

CC

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

I/O

n

DSR, D CP, S MR, S OE

n

SL

0

1

0.25

0.60

0.25

0.30

December 1990 8

Philips Semiconductors Product speciﬁcation

8-bit universal shift register; 3-state 74HC/HCT299

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

t

PHL

/ t

propagation delay

PLH

CP to Q0, Q

t

PHL

t

PHL

/ t

propagation delay

PLH

CP to I/O

propagation delay

n

MR to Q0, Q7 or I/O

t

PZH

t

PHZ

t

PLZ

t

THL

/ t

3-state output enable time

PZL

OEn to I/O

n

3-state output disable time

OEn to I/O

n

3-state output disable time

OEn to I/O

output transition time

TLH

n

bus driver (I/On)

t

THL

/ t

output transition time

TLH

standard (Q0, Q7)

t

W

clock pulse width

HIGH or LOW

t

W

master reset pulse width

LOW

t

rem

removal time

MR to CP

t

su

set-up time

I/On, DSR, DSL to CP

t

su

set-up time

S0, S1to CP

t

h

hold time

I/On, DSR, DSL to CP

t

h

hold time

S0, S1 to CP

f

max

maximum clock pulse

frequency

T

amb

(°C)

TEST CONDITIONS

74HCT

+25 −40 to +85 −40 to +125

UNIT

min. typ. max. min. max. min. max.

WAVEFORMS

V

CC

(V)

22 37 46 56 ns 4.5 Fig.6

7

22 37 46 56 ns 4.5 Fig.6

27 46 58 69 ns 4.5 Fig.7

n

19 30 38 45 ns 4.5 Fig.9

24 37 46 56 ns 4.5 Fig.9

20 32 40 48 ns 4.5 Fig.9

5 12 15 18 ns 4.5 Fig.6

7 15 19 22 ns 4.5 Fig.6

20 10 25 30 ns 4.5 Fig.6

20 11 25 30 ns 4.5 Fig.7

10 2 9 11 ns 4.5 Fig.7

25 14 31 38 ns 4.5 Fig.6

32 18 40 48 ns 4.5 Fig.8

0 −11 0 0 ns 4.5 Fig.6

0 −17 0 0 ns 4.5 Fig.8

25 42 20 17 MHz 4.5 Fig.6

December 1990 9

Philips Semiconductors Product speciﬁcation

8-bit universal shift register; 3-state 74HC/HCT299

AC WAVEFORMS

handbook, full pagewidth

The shaded areas indicate when the input is permitted to change for predictable output performance.

(1) HC : V

HCT : V

= 50%; VI= GND to VCC.

M

= 1.3 V; VI= GND to 3 V.

M

I/O ,D ,D

SR SL

n INPUTS

CP INPUT

I/O ,Q ,Q

n0 7

OUTPUTS

MBA335

(1)

V

M

t

su

t

h

(1)

V

M

t

PHL

1/ f

max

t

W

(1)

V

M

t

THL

t

su

t

h

t

PLH

t

TLH

Fig.6 Waveforms showing the clock (CP) to output (I/On, Q0, Q7) propagation delays, the clock pulse width, the

I/On, DSR and DSL to CP set-up and hold times, the output transition times and the maximum clock frequency.

(1) HC : VM= 50%; VI= GND to VCC.

HCT : V

= 1.3 V; VI= GND to 3 V.

M

Fig.7 Waveforms showing the master reset (MR) pulse width (LOW), the master reset to output (I/On, Q0, Q7)

propagation delays and the master reset to clock (CP) removal time.

December 1990 10

Philips Semiconductors Product speciﬁcation

8-bit universal shift register; 3-state 74HC/HCT299

(1) HC : VM= 50%; VI= GND to VCC.

HCT : V

= 1.3 V; VI= GND to 3 V.

M

Fig.8 Waveforms showing the set-up and hold times from the mode control inputs (S0, S1) to the clock (CP).

(1) HC : VM= 50%; VI= GND to VCC.

HCT : V

= 1.3 V; VI= GND to 3 V.

M

Fig.9 Waveforms showing the 3-state enable and disable times for OEn inputs.

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.

December 1990 11