Datasheet 74 hct283 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT283

4-bit binary full adder with fast carry

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product speciﬁcation

4-bit binary full adder with fast carry 74HC/HCT283

FEATURES

• High-speed 4-bit binary addition

• Cascadable in 4-bit increments

• Fast internal look-ahead carry

• Output capability: standard

• ICC category: MSI

CIN+ (A1+ B1) +2(A2+ B2) ++4(A3+ B3) + 8(A4+ B4)= =∑1+2∑2+4∑3+8∑4+16C

Where (+) = plus. Due to the symmetry of the binary add function, the “283”

can be used with either all active HIGH operands (positive logic) or all active LOW operands (negative logic); see function table. In case of all active LOW operands the results ∑1 to ∑4 and C

GENERAL DESCRIPTION

active LOW. With active HIGH inputs, CIN must be held LOW when no “carry in” is intended. Interchanging inputs

The 74HC/HCT283 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL

of equal weight does not affect the operation, thus CIN, A1, B1 can be assigned arbitrarily to pins 5, 6, 7, etc.

(LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT283 add two 4-bit binary words (A

plus Bn)

n

See the “583” for the BCD version.

plus the incoming carry. The binary sum appears on the sum outputs (∑1 to ∑4) and the out-going carry (C

OUT

)

according to the equation:

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

C C

I PD

/ t

PLH

propagation delay CL= 15 pF; VCC=5 V

C

to ∑

IN

1

C

to ∑

IN

2

C

to ∑

IN

3

C

to ∑

IN

4

A

or Bn to ∑

n

C

to C

IN

or Bn to C

A

n

OUT

input capacitance 3.5 3.5 pF power dissipation capacitance per package notes 1 and 2 88 92 pF

OUT

should be interpreted also as

OUT

TYPICAL

HC HCT

16 15 ns 18 21 ns 20 23 ns 23 27 ns 21 25 ns 20 23 ns 20 24 ns

UNIT

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

December 1990 2

Philips Semiconductors Product speciﬁcation

4-bit binary full adder with fast carry 74HC/HCT283

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

4, 1, 13, 10 ∑ 5, 3, 14, 12 A 6, 2, 15, 11 B 7C

to ∑

1

to A

1

to B

1

IN

4 4 4

sum outputs A operand inputs B operand inputs

carry input 8 GND ground (0 V) 9C 16 V

OUT

CC

carry output

positive supply voltage

.

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product speciﬁcation

4-bit binary full adder with fast carry 74HC/HCT283

Fig.4 Functional diagram.

FUNCTION TABLE

PINS CINA1A2A

A4B1B

3

2

B3B

4

∑1∑

∑

2

3

C

4

OUT

logic levels L L H L H H L L H H H L L H active HIGH 0 0 1 0 1 1 0 0 1 1 1001 active LOW 1 1 0 1 0 0 1 1 0 0 0110

Note

1. H = HIGH voltage level L = LOW voltage level

2. example

1001 1010

----10011

3. for active HIGH, example = (9 + 10 = 19)

4. for active LOW, example = (carry + 6 + 5 = 12)

EXAMPLE

(3) (4)

(2)

December 1990 4

Philips Semiconductors Product speciﬁcation

4-bit binary full adder with fast carry 74HC/HCT283

Fig.5 Logic diagram.

December 1990 5

Philips Semiconductors Product speciﬁcation

4-bit binary full adder with fast carry 74HC/HCT283

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

t

PHL

t

PHL

t

PHL

t

PHL

t

PHL

t

PHL

t

PHL

t

THL

/ t

propagation delay

PLH

CIN to ∑

propagation delay

PLH

CIN to ∑

propagation delay

PLH

CIN to ∑

propagation delay

PLH

CIN to ∑

propagation delay

PLH

An or Bn to ∑

propagation delay

PLH

CIN to C

propagation delay

PLH

An or Bn to C

output transition time 19

TLH

1

2

3

4

n

OUT

(°C)

T

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

52 19 15

58 21 17

63 23 18

74 27 22

69 25 20

63 23 18

160 32 27

180 36 31

195 39 33

230 46 39

210 42 36

195 39 33

75

7

15

6

13

200 40 34

225 45 38

245 49 42

290 58 49

265 53 45

245 49 42

95 19 16

240 48 41

270 54 46

295 59 50

345 69 59

315 63 54

295 59 50

110 22 19

.

UNIT

ns 2.0

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0

December 1990 6

Philips Semiconductors Product speciﬁcation

4-bit binary full adder with fast carry 74HC/HCT283

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: standard ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I

) for a unit load of 1 is given in the family specifications.

CC

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

C

IN

B2, A2, A B

1

B

, A4, A3, B

4

1

3

1.50

1.00

0.40

0.50

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

T

amb

(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

+25 −40 to +85 −40 to +125

UNIT

V

(V)

CC

min. typ. max. min. max. min. max.

t

PHL

t

PHL

t

PHL

t

PHL

t

PHL

t

PHL

t

PHL

t

THL

/ t

propagation delay

PLH

CIN to ∑

propagation delay

PLH

CIN to ∑

propagation delay

PLH

CIN to ∑

propagation delay

PLH

CIN to ∑

propagation delay

PLH

An or Bn to ∑

propagation delay

PLH

CIN to C

propagation delay

PLH

An or Bn to C

output transition time 7 15 19 22 ns 4.5 Fig.6

TLH

1

2

3

4

n

OUT

18 31 39 47 ns 4.5 Fig.6

25 43 54 65 ns 4.5 Fig.6

27 46 58 69 ns 4.5 Fig.6

31 53 66 80 ns 4.5 Fig.6

29 49 61 74 ns 4.5 Fig.6

27 46 58 69 ns 4.5 Fig.6

28 48 60 72 ns 4.5 Fig.6

WAVEFORMS

December 1990 7

Philips Semiconductors Product speciﬁcation

4-bit binary full adder with fast carry 74HC/HCT283

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

HCT: VM= 1.3 V; VI= GND to 3 V.

Fig.6 Waveforms showing the inputs (CIN, An, Bn)

to the outputs (∑n, C

) propagation delays

OUT

and the output transition times.

APPLICATION INFORMATION

Fig.7 3-bit adder.

Fig.8 2-bit and 1-bit adder.

Fig.9 5-input encoder.

Notes to Figs 7 to 10 Figure 7 shows a 3-bit adder using the “283”. Tying the

operand inputs of the fourth adder (A3, B3) LOW makes ∑

3

dependent on, and equal to, the carry from the third adder. Based on the same principle, Figure 8 shows a method of dividing the “283” into a 2-bit and 1-bit adder. The third stage adder (A2, B2, ∑ 2) is used simply as means of transferring the carry into the fourth stage (via A2 and B2) and transferring the carry from the second stage on ∑2. Note that as long as long as A2 and B2 are the same, HIGH or LOW, they do not influence ∑2. Similarly, when A2 and B2 are the same, the carry into the third stage does not influence the carry out of the third stage. Figure 9 shows a method of implementing a 5-input encoder, where the

December 1990 8

Fig.10 5-input majority gate.

inputs are equally weighted. The outputs ∑

, ∑1 and ∑

0

2

produce a binary number equal to the number inputs (I1 to I5) that are HIGH. Figure 10 shows a method of implementing a 5-input majority gate. When three or more inputs (I1 to I5) are HIGH, the output M5 is HIGH.

PACKAGE OUTLINES

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

See

.