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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT273
Octal D-type flip-flop with reset;
positive-edge trigger
Product specification
File under Integrated Circuits, IC06
September 1993
Page 2
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
FEATURES
• Ideal buffer for MOS microprocessor or memory
• Common clock and master reset
• Eight positive edge-triggered D-type flip-flops
• See “377” for clock enable version
• See “373” for transparent latch version
• See “374” for 3-state version
• Output capability; standard
• ICC category: MSI
74HC/HCT273
GENERAL DESCRIPTION
The 74HC/HCT273 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW voltage level on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/ tPLH
f
max
C
I
C
PD
propagation delay CL= 15 pF; VCC=5 V
CP to Q
MR to Q
n
n
maximum clock frequency 66 36 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per flip-flop notes 1 and 2 20 23 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
TYPICAL
UNIT
HC HCT
15 15 ns
15 20 ns
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
September 1993 2
.
Page 3
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
74HC/HCT273
positive-edge trigger
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
2, 5, 6, 9, 12, 15, 16, 19 Q
3, 4, 7, 8, 13, 14, 17, 18 D
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge-triggered)
20 V
MR master reset input (active LOW)
to Q
0
to D
0
CC
7
7
flip-flop outputs
data inputs
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
September 1993 3
Page 4
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74HC/HCT273
FUNCTION TABLE
OPERATING
MODES
reset (clear) L X X L
load “1” H ↑ hH
load “0” H ↑ IL
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
↑ = LOW-to-HIGH transition
X = don’t care
INPUTS OUTPUTS
MR CP D
n
Q
n
Fig.4 Functional diagram.
Fig.5 Logic diagram.
September 1993 4
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Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
THL
t
W
/ t
/ t
propagation delay
PLH
CP to Q
n
propagation delay
MR to Q
output transition time 19
TLH
n
clock pulse width
HIGH or LOW
t
W
master reset pulse width
LOW
t
rem
removal time
MR to CP
t
su
set-up time
Dn to CP
t
h
hold time
Dn to CP
f
max
maximum clock pulse
frequency
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
min. typ. max. min. max. min. max.
80
16
14
60
12
10
50
10
9
60
12
10
3
3
3
6.0
30
35
(°C)
T
amb
74HC
+25 −40 to +85 −40 to +125
41
15
13
44
16
14
7
6
14
5
4
17
6
5
−6
−2
−2
11
4
3
−6
−2
−2
20.6
103
122
150
30
26
150
30
26
75
15
13
100
20
17
75
15
13
65
13
11
75
15
13
3
3
3
4.8
24
28
185
37
31
185
37
31
95
19
15
225
45
38
225
45
38
110
22
19
120
24
20
90
18
15
75
15
13
90
18
15
3
3
3
4.0
20
24
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
74HC/HCT273
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.6
4.5
6.0
September 1993 5
Page 6
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
74HC/HCT273
positive-edge trigger
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
MR
CP
D
n
1.00
1.75
0.15
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
) for a unit load of 1 is given in the family specifications.
CC
.
SYMBOL PARAMETER
t
PHL
t
PHL
t
THL
t
W
/ t
/ t
propagation delay
PLH
CP to Q
n
propagation delay
MR to Q
output transition time 7 15 19 22 ns 4.5 Fig.6
TLH
n
clock pulse width
HIGH or LOW
t
W
master reset pulse width
LOW
t
rem
removal time
MR to CP
t
su
set-up time
Dn to CP
t
h
hold time
Dn to CP
f
max
maximum clock pulse
frequency
T
amb
(°C)
TEST CONDITIONS
74HCT
+25 −40 to +85 −40 to +125
UNIT
WAVEFORMS
V
CC
(V)
min. typ. max. min. max. min. max.
16 30 38 45 ns 4.5 Fig.6
23 34 43 51 ns 4.5 Fig.7
16 9 20 24 ns 4.5 Fig.6
16 8 20 24 ns 4.5 Fig.7
10 −2 13 15 ns 4.5 Fig.7
12 5 15 18 ns 4.5 Fig.8
3 −4 3 3 ns 4.5 Fig.8
30 56 24 20 MHz 4.5 Fig.6
September 1993 6
Page 7
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
74HC/HCT273
positive-edge trigger
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width output
= 1.3 V; VI= GND to 3 V.
HCT: V
M
transition times and the maximum clock pulse frequency.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.7 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays
and the master reset to clock (CP) removal time.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.8 Waveforms showing the data set-up and hold times for the data input (Dn).
September 1993 7
Page 8
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
74HC/HCT273
.
September 1993 8
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