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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT259
8-bit addressable latch
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
FEATURES
• Combines demultiplexer and 8-bit latch
• Serial-to-parallel capability
• Output from each storage bit available
• Random (addressable) data entry
• Easily expandable
• Common reset input
• Useful as a 3-to-8 active HIGH decoder
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT259 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT259 are high-speed 8-bit addressable
latches designed for general purpose storage applications
in digital systems. The “259” are multifunctional devices
capable of storing single-line data in eight addressable
latches, and also 3-to-8 decoder and demultiplexer, with
active HIGH outputs (Q
to Q7), functions are available.
0
The “259” also incorporates an active LOW common reset
(MR) for resetting all latches, as well as, an active LOW
enable input (LE).
The “259” has four modes of operation as shown in the
mode select table. In the addressable latch mode, data on
the data line (D) is written into the addressed latch. The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states.
In the memory mode, all latches remain in their previous
states and are unaffected by the data or address inputs.
In the 3-to-8 decoding or demultiplexing mode, the
addressed output follows the state of the D input with all
other outputs in the LOW state. In the reset mode all
outputs are LOW and unaffected by the address (A0 to A2)
and data (D) input. When operating the “259” as an
addressable latch, changing more than one bit of address
could impose a transient-wrong address. Therefore, this
should only be done while in the memory mode. The mode
select table summarizes the operations of the “259”.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/ tPLH
t
PHL
C
I
C
PD
propagation delay CL= 15 pF; VCC=5 V
D to Q
n
A
, LE to Q
n
MR to Q
n
n
input capacitance 3.5 3.5 pF
power dissipation capacitance per latch notes 1 and 2 19 19 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
TYPICAL
UNIT
HC HCT
18 20 ns
17 20 ns
15 20 ns
December 1990 2
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Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3 A
4, 5, 6, 7, 9 10, 11, 12 Q
to A
0
to Q
0
2
7
8 GND ground (0 V)
13 D data input
14
15
16 V
LE latch enable input (active LOW)
MR conditional reset input (active LOW)
CC
.
address inputs
latch outputs
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
Fig.4 Functional diagram.
MODE SELECT TABLE
LE MR MODE
L
H
addressable latch
H
H
memory
L
L
active HIGH 8-channel demultiplexer
H
L
reset
December 1990 4
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Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
FUNCTION TABLE
OPERATING
MODES
MR LE D A
INPUTS OUTPUTS
A
A
0
1
Q
2
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
6
master reset L H X X X X L L L L L L L L
L
L
d
L
L
L
demultiplex
Q=d
L
L
d
H
L
L
L
L
L
d
L
H
L
L
L
L
d
H
H
L
L
L
Q=d
L
L
L
L
Q=d
L
L
L
L
Q=d
L
L
L
L
L
L
L
L
L
L
L
L
(active HIGH)
decoder
(when D = H)
L
L
d
H
L
H
L
L
d
L
H
H
L
L
d
H
H
H
store (do nothing) H H X X X X q
H
L
d
L
L
L
H
L
d
H
L
L
H
L
d
L
H
L
H
L
d
H
H
L
L
L
L
L
Q=d
q
q
q
L
L
L
L
q
0
q
Q=d
0
q
0
q
0
L
L
L
L
q
1
q
1
q
Q=d
1
q
1
L
L
L
L
q
2
q
2
q
2
q
Q=d
2
Q=d
L
L
L
q
3
q
3
q
3
q
3
q
L
Q=d
L
L
q
4
q
4
q
4
q
4
q
4
L
L
Q=d
L
q
5
5
5
5
5
6
q
6
q
6
q
6
q
6
L
L
d
L
L
H
addressable latch
H
L
d
L
L
H
q
H
L
d
H
L
H
q
H
L
d
L
H
H
q
H
L
d
H
H
H
q
q
0
q
0
q
0
q
0
q
1
q
1
q
1
q
1
q
2
q
2
q
2
q
2
Q=d
3
q
3
q
3
q
3
q
Q=d
4
q
4
q
4
q
5
5
5
6
q
6
Q=d
q
6
Q
L
L
L
L
L
L
L
Q=d
q
7
q
7
q
7
q
7
q
7
q
7
q
7
q
7
Q=d
7
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition
q = lower case letters indicate the state of the referenced output established during the last cycle in which it was
addressed or cleared
December 1990 5
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Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
Fig.5 Logic diagram.
December 1990 6
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Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
PHL
t
PHL
t
THL
t
W
/ t
/ t
/ t
/ t
propagation delay
PLH
D to Q
n
propagation delay
PLH
An to Q
propagation delay
PLH
LE to Q
n
n
propagation delay
MR to Q
output transition time 19
TLH
n
LE pulse width
HIGH or LOW
t
W
MR pulse width
LOW
t
su
set-up time
D, An to LE
t
h
hold time
D to LE
t
h
hold time
An to LE
(°C)
T
amb
74HC
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
58
70
14
12
70
14
12
80
16
14
0
0
0
2
2
2
21
17
58
21
17
55
20
16
50
18
14
7
6
17
6
5
17
6
5
19
7
6
−19
−6
−5
−11
−4
−3
185
37
31
185
37
31
170
34
29
155
31
26
75
15
13
90
18
15
90
18
15
100
20
17
0
0
0
2
2
2
230
46
39
230
46
39
215
43
37
195
39
33
95
19
16
280
56
48
280
56
48
255
51
43
235
47
40
119
22
19
105
21
18
105
21
18
120
24
20
0
0
0
2
2
2
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.6
4.5
6.0
Fig.9
4.5
6.0
Figs 6 and 7
4.5
6.0
Fig.6
4.5
6.0
Fig.9
4.5
6.0
Figs 10 and 11
4.5
6.0
Fig.10
4.5
6.0
Fig.11
4.5
6.0
December 1990 7
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Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
A
n
LE
D
MR
1.50
1.50
1.20
0.75
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
) for a unit load of 1 is given in the family specifications.
CC
.
December 1990 8
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Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
PHL
t
PHL
t
THL
t
W
/ t
/ t
/ t
/ t
propagation delay
PLH
D to Q
n
propagation delay
PLH
An to Q
propagation delay
PLH
LE to Q
n
n
propagation delay
MR to Q
output transition time 7 15 19 22 ns 4.5 Figs 6 and 7
TLH
n
LE pulse width
LOW
t
W
MR pulse width
LOW
t
su
set-up time
D to LE
t
su
set-up time
An to LE
t
h
hold time
D to LE
t
h
hold time
An to LE
T
amb
(°C)
TEST CONDITIONS
74HCT
+25 −40 TO +85 −40 TO +125
UNIT
WAVEFORMS
V
CC
(V)
min. typ. max. min. max. min. max.
23 39 49 59 ns 4.5 Fig.7
25 41 51 62 ns 4.5 Fig.8
22 38 48 57 ns 4.5 Fig.6
23 39 49 59 ns 4.5 Fig.9
19 11 24 29 ns 4.5 Fig.6
18 10 23 27 ns 4.5 Fig.9
17 10 21 26 ns 4.5 Fig.10
17 10 21 26 ns 4.5 Fig.11
0 −8 0 0 ns 4.5 Fig.10
0 −4 0 0 ns 4.5 Fig.11
December 1990 9
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Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.6 Waveforms showing the enable input (LE) to output (Qn) propagation delays, the enable input pulse width
and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.7 Waveforms showing the data input (D) to output (Qn) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.8 Waveforms showing the address inputs (An) to outputs (Qn) propagation delays and the output transition
times.
December 1990 10
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Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.9 Waveforms showing the conditional reset input (MR) to output (Qn) propagation delays.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.11 Waveforms showing the address set-up and hold times for An inputs to LE input.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 11
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