Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT251
8-input multiplexer; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
FEATURES
• True and complement outputs
• Both outputs are 3-state for further multiplexer
expansion
• Multifunction capability
• Permits multiplexing from n-lines to one line
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT251 are high-speed Si-gate CMOS devices
The 74HC/HCT251 are the logic implementations of
single-pole 8-position switches with the state of three
select inputs (S
Assertion (Y) and negation (Y) outputs are both provided.
The output enable input (OE) is active LOW. The logic
function provided at the output, when activated, is:
Y=OE.(I0.S0.S1.S2 + I1.S0.S1.S2+
+ I2.S0.S1.S2+ I3.S0.S1.S2+
+ I4.S0.S1.S2+ I5.S0.S1.S2+
+ I6.S0.S1.S2+ I7.S0.S1.S2)
Both outputs are in the high impedance OFF-state (Z)
when the output enable input is HIGH, allowing multiplexer
expansion by tying the outputs.
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
= 25 °C; tr= tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
/ t
t
PHL
PLH
C
I
C
PD
propagation delay CL= 15 pF; VCC= 5 V
I
to Y 15 19 ns
n
I
to Y1719ns
n
to Y 20 20 ns
S
n
S
to Y2121ns
n
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 44 46 pF
0,S1,S2
) controlling the switch positions.
TYPICAL
UNIT
HC HCT
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW):
PD
PD= CPD× V
2
× fi+∑(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
December 1990 2
.
Page 3
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
4, 3, 2, 1, 15, 14, 13, 12 I
5 Y multiplexer output
6
7
8 GND ground (0 V)
11, 10, 9 S
16 V
to I
0
7
multiplexer inputs
Y complementary multiplexer output
OE 3-state output enable input (active LOW)
0,S1,S2
CC
select inputs
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
Page 4
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
FUNCTION TABLE
INPUTS OUTPUTS
OE S
S
2
S
1
0
I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
YY
HXXXXXXXXXXXZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Fig.4 Functional diagram. Fig.5 Logic diagram.
December 1990 4
Page 5
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICCcategory: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= tf= 6 ns; CL= 50 pF
r
SYMBOL PARAMETER
t
PHL
/ t
propagation delay
PLH
Into Y
t
PHL
/ t
propagation delay
PLH
Into Y
t
PHL
/ t
propagation delay
PLH
Snto Y
t
PHL
/ t
propagation delay
PLH
Snto Y
t
PZH
/ t
3-state output enable time
PZL
OE to Y, Y
t
PHZ
/ t
3-state output disable time
PLZ
OE to Y, Y
t
THL
/ t
output transition time 19
TLH
(°C)
T
amb
74HC
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
50
18
14
55
20
16
66
24
19
69
25
20
36
13
10
39
14
11
7
6
170
34
29
175
35
30
205
41
35
205
41
35
140
28
24
140
28
24
75
15
13
215
43
37
220
44
37
255
51
43
255
51
43
175
35
30
170
35
30
95
19
16
255
51
43
265
53
45
310
62
53
310
62
53
210
42
36
210
42
36
110
22
19
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Figs 6 and 7
4.5
6.0
December 1990 5
Page 6
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
I
n
S
0
S1,S
OE
2
1.00
1.50
1.50
1.50
AC CHARACTERISTICS FOR HCT
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
T
amb
(°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25 −40 to +85 −40 to +125
UNIT
V
(V)
min. typ. max. min. max. min. max.
t
PHL
/ t
propagation delay
PLH
22 35 44 53 ns 4.5 Fig.6
Into Y
t
PHL
/ t
propagation delay
PLH
22 35 44 53 ns 4.5 Fig.7
Into Y
t
PHL
/ t
propagation delay
PLH
24 44 55 66 ns 4.5 Fig.6
Snto Y
t
PHL
/ t
propagation delay
PLH
25 44 55 66 ns 4.5 Fig.7
Snto Y
t
PZH
/ t
3-state output enable time
PZL
13 28 35 42 ns 4.5 Fig.7
OE to Y, Y
t
PHZ
/ t
3-state output disable time
PLZ
14 28 35 42 ns 4.5 Fig.7
OE to Y, Y
t
THL
/ t
output transition time 7 15 19 22 ns 4.5 Figs 6 and 7
TLH
WAVEFORMS
CC
December 1990 6
Page 7
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3V; VI= GND to 3 V.
HCT: V
M
Fig.6 Waveforms showing the multiplexer input (In) and select input (Sn) to output (Y) propagation delays and
the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3V; VI= GND to 3 V.
HCT: V
M
Fig.7 Waveforms showing the multiplexer input (In) and select input (Sn) to output (Y) propagation delays and
the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3V; VI= GND to 3 V.
HCT: V
M
Fig.8 Waveforms showing the 3-state enable and disable times.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 7
Loading...