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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT21
Dual 4-input AND gate
Product specification
File under Integrated Circuits, IC06
December 1990
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Philips Semiconductors Product specification
Dual 4-input AND gate 74HC/HCT21
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT21 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT21 provide the 4-input AND function.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
C
C
I
PD
/ t
PLH
propagation delay nA, nB, nC, nD to nY CL= 15 pF; VCC= 5 V 10 12 ns
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 15 16 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi + ∑ (CL× V
CC
2
× fO) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC= supply voltage in V
∑ (CL× V
2. For HC the condition is VI= GND to V
2
× fo) = sum of outputs
CC
CC
For HCT the condition is VI= GND to VCC− 1.5 V
TYPICAL
UNIT
HC HCT
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
December 1990 2
.
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Philips Semiconductors Product specification
Dual 4-input AND gate 74HC/HCT21
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 9 1A, 2A data inputs
2, 10 1B, 2B data inputs
3, 11 n.c. not connected
4, 12 1C, 2C data inputs
5, 13 1D, 2D data inputs
6, 8 1Y, 2Y data outputs
7 GND ground (0 V)
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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Philips Semiconductors Product specification
Dual 4-input AND gate 74HC/HCT21
Fig.4 Functional diagram. Fig.5 Logic diagram (one gate).
FUNCTION TABLE
INPUTS OUTPUT
nA nB nC nD nY
LXXX L
XLXX L
X XLX L
XXXL L
HHHH H
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
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Philips Semiconductors Product specification
Dual 4-input AND gate 74HC/HCT21
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
/ t
propagation delay
PLH
nA, nB, nC, nD to nY
t
THL
/ t
output transition time 19 75 95 110 ns 2.0 Fig.6
TLH
.
(°C) TEST CONDITIONS
T
amb
74HC
UNIT
+25 −40 to+85 −40 to+125
min. typ. max. min. max. min. max.
33 110 140 165 ns 2.0 Fig.6
12 22 28 33 4.5
10 19 24 28 6.0
7 15 19 22 4.5
6 13 16 19 6.0
V
(V)
CC
WAVEFORMS
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Philips Semiconductors Product specification
Dual 4-input AND gate 74HC/HCT21
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: SSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
nA, nB, 1.50
nC, nD 1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
(°C) TEST CONDITIONS
T
amb
74HCT
SYMBOL PARAMETER
+25 −40 to+85 −40 to+125
UNIT
V
(V)
CC
min. typ. max. min. max. min. max.
t
PHL
/ t
propagation delay
PLH
15 27 34 41 ns 4.5 Fig.6
nA, nB nC, nD to nY
t
THL
/ t
output transition time 7 15 19 22 ns 4.5 Fig.6
TLH
WAVEFORMS
AC WAVEFORMS
(1) HC: VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.6 Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output transition
times.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 6
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