Datasheet 74 hct193 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT193

Presettable synchronous 4-bit binary up/down counter

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary up/down counter

FEATURES

• Synchronous reversible 4-bit binary counting

• Asynchronous parallel load

• Asynchronous reset

• Expandable without external logic

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT193 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT193 are 4-bit synchronous binary up/down counters. Separate up/down clocks, CP CPDrespectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPUclock is pulsed while CPDis held HIGH, the device will count up. If the CPDclock is pulsed while CPUis held HIGH, the device will count down. Only one clock input can be held HIGH at any time, or erroneous operation will result. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL).

The “193” contains four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions.

Each flip-flop contains JK feedback from slave to master, such that a LOW-to-HIGH transition on the CPDinput will decrease the count by one, while a similar transition on the CPUinput will advance the count by one.

U

and

74HC/HCT193

One clock should be held HIGH while counting with the other, otherwise the circuit will either count by two’s or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either clock input is LOW. Applications requiring reversible operation must make the reversing decision while the activating clock is HIGH to avoid erroneous counts.

The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPUwill cause TCUto go LOW.

TCUwill stay LOW until CPUgoes HIGH again, duplicating the count up clock.

Likewise, the TCDoutput will go LOW when the circuit is in the zero state and the CPDgoes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added.

The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0to D3) is loaded into the counter and appears on the outputs (Q0to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted.

December 1990 2

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary up/down counter

QUICK REFERENCE DATA

GND = 0 V; T

SYMBOL PARAMETER CONDITIONS

t

/ t

PHL

PLH

f

max

C

I

C

PD

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD= CPD× V fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V CL= output load capacitance in pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V For HCT the condition is VI= GND to VCC− 1.5 V

= 25 °C; tr= tf= 6 ns

amb

propagation delay CPD, CPU to Q maximum clock frequency 45 47 MHz

n

CL= 15 pF; VCC= 5 V

input capacitance 3.5 3.5 pF power dissipation capacitance per package notes 1 and 2 24 26 pF

2

× fi+∑(CL× V

CC

2

× fo) = sum of outputs

CC

2

× fo) where:

CC

74HC/HCT193

TYPICAL

UNIT

HC HCT

20 20 ns

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 3

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary up/down counter

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

3, 2, 6, 7 Q 4CP 5CP 8 GND ground (0 V) 11 12 13 14 MR asynchronous master reset input (active HIGH) 15, 1, 10, 9 D 16 V

Note

1. LOW-to-HIGH, edge triggered

to Q

0

3 D U

ﬂip-ﬂop outputs count down clock input count up clock input

(1)

PL asynchronous parallel load input (active LOW) TC TC

U D

to D

0

CC

3

terminal count up (carry) output (active LOW) terminal count down (borrow) output (active LOW)

data inputs positive supply voltage

74HC/HCT193

Fig.1 Pin configuration. Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990 4

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary

74HC/HCT193

up/down counter

FUNCTION TABLE

OPERATING MODE

reset (clear)

parallel load

count up L H ↑ H X X X X count up H count down L H H ↑ X X X X count down H H

Notes

1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH clock transition

2. TCU=CPUat terminal count up (HHHH)

3. TCD=CPDat terminal count down (LLLL)

MR PL CPUCPDD0D1D2D

H

X

H

X

L

INPUTS OUTPUTS

Q

3

X

L

XXXXXXX

X

H

X

L

X

H

L

X

H

X

H

L

X

L

H

Q1Q2Q3TCUTC

0

LLL

L L H H

LLH

L L

L H H

H

L

H

L

H

L

H

(2)

D

L H

L H H H

H

(3)

Fig.4 Functional diagram.

December 1990 5

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary up/down counter

(1) Clear overrides load, data and

count inputs.

(2) When counting up the count down

clock input (CP when counting down the count up clock input (CP

Sequence

Clear (reset outputs to zero); load (preset) to binary thirteen; count up to fourteen, fifteen,

terminal count up, zero, one and two;

count down to one, zero,

terminal count down, fifteen,

) must be HIGH,

D

) must be HIGH.

U

74HC/HCT193

Fig.5 Typical clear, load and count sequence.

Fig.6 Logic diagram.

December 1990 6

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary up/down counter

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see Output capability: standard

ICCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= tf= 6 ns; CL= 50 pF

r

SYMBOL PARAMETER

t

PHL

/ t

propagation delay

PLH

CPU,CPDto Q

t

PHL

/ t

propagation delay

PLH

CPUto TC

t

PHL

/ t

propagation delay

PLH

CPDto TC

t

PHL

t

PHL

t

PHL

t

PHL

/ t

propagation delay

PLH

PL to Q

propagation delay

MR to Q

propagation delay

PLH

Dnto Q

propagation delay

PLH

n

PL to TCU, PL to TC

t

PHL

/ t

propagation delay

PLH

MR to TCU,MRtoTC

t

PHL

/ t

propagation delay

PLH

Dnto TCU,Dnto TC

t

THL

t

W

/ t

output transition time 19

TLH

up, down clock pulse

width HIGH or LOW

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

63

n

23 18

39

U

14 11

39

D

14 11

69 25 20

58 21 17

69 25 20

80

D

29 23

74

D

27 22

80

D

29 23

7 6

100

22

20

8

17

6

215 43 37

125 25 21

220 44 37

200 40 34

210 42 36

290 58 49

285 57 48

290 58 49

75 15 13

T

amb

125 25 21

(°C)

74HC

270 54 46

155 31 26

275 55 47

250 50 43

265 53 45

365 73 62

355 71 60

365 73 62

95 19 16

150 30 26

325 65 55

190 38 32

330 66 56

300 60 51

315 63 54

435 87 74

430 86 73

435 87 74

110 22 19

.

UNIT

ns 2.0

74HC/HCT193

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.7

4.5

6.0 Fig.8

4.5

6.0 Fig.8

4.5

6.0 Fig.9

4.5

6.0 Fig.10

4.5

6.0 Fig.9

4.5

6.0 Fig.12

4.5

6.0 Fig.12

4.5

6.0 Fig.12

4.5

6.0 Fig.10

4.5

6.0 Fig.7

4.5

6.0

December 1990 7

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary up/down counter

SYMBOL PARAMETER

t

W

master reset pulse width

HIGH

t

W

parallel load pulse width

LOW

t

rem

removal time

PL to CPU,CP

t

rem

removal time

MR to CPU,CP

t

su

set-up time

Dnto PL

t

h

hold time

Dnto PL

t

h

hold time

CPUto CPD,

f

max

CPDto CP

maximum up, down clock

U

pulse frequency

100 20 17

50

D

10 9

50

D

10 9

80 16 14

0 0 0

80 16 8

4.0 20 24

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

25 9 7

19 7 6

8 3 2

0 0 0

22 8 6

−14

−5

−4

22 8 6

13.5 41 49

T

amb

125 25 21

65 13 11

100 20 17

0 0 0

100 20 17

3.2 16 19

(°C)

74HC

150 30 26

75 15 13

120 24 20

0 0 0

120 24 20

2.6 13 15

74HC/HCT193

TEST CONDITIONS

UNIT

ns 2.0

MHz 2.0

WAVEFORMS

V

CC

(V)

Fig.10

4.5

6.0 Fig.9

4.5

6.0 Fig.9

4.5

6.0 Fig.10

4.5

6.0 Fig.11 note:

4.5

CPU= CPD=

6.0

HIGH Fig.11

4.5

6.0 Fig.13

4.5

6.0 Fig.7

4.5

6.0

December 1990 8

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary

74HC/HCT193

up/down counter

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see Output capability: standard

ICCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I To determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

D

n

CPU,CP PL MR

D

0.35

1.40

0.65

1.05

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

) for a unit load of 1 is given in the family specifications.

CC

.

December 1990 9

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary up/down counter

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

SYMBOL PARAMETER

/ t

t

PHL

PLH

t

/ t

PHL

PLH

t

/ t

PHL

PLH

/ t

t

PHL

PLH

t

PHL

t

/ t

PHL

PLH

t

/ t

PHL

PLH

t

/ t

PHL

PLH

t

/ t

PHL

PLH

t

/ t

THL

TLH

= tf= 6 ns; CL= 50 pF

r

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

propagation delay

CPU,CPDto Q

n

propagation delay

CPUto TC

U

propagation delay

CPDto TC

D

propagation delay

PL to Q

n

propagation delay

MR to Q

n

propagation delay

Dn to Q

n

propagation delay

PL to TCU, PL to TC

propagation delay

MR to TCU, MR to TC

propagation delay

Dn to TCU,Dnto TC

D

23 43 54 65 ns 4.5 Fig.7

15 27 34 41 ns 4.5 Fig.8

26 46 58 69 ns 4.5 Fig.9

22 40 50 60 ns 4.5 Fig.10

27 46 58 69 ns 4.5 Fig.9

31 55 69 83 ns 4.5 Fig.12

29 55 69 83 ns 4.5 Fig.12

32 58 73 87 ns 4.5 Fig.12

output transition time 7 15 19 22 ns 4.5 Fig.10

T

amb

74HCT

(°C)

74HC/HCT193

TEST CONDITIONS

UNIT

WAVEFORMS

V

CC

(V)

t

W

up, down clock pulse width

25 11 31 38 ns 4.5 Fig.7

HIGH or LOW

t

W

master reset pulse width

20 7 25 30 ns 4.5 Fig.10

HIGH

t

W

parallel load pulse width

20 8 25 30 ns 4.5 Fig.9

LOW

t

rem

su

removal time

PL to CPU,CP

removal time

MR to CPU,CP

set-up time

10 2 13 15 ns 4.5 Fig.9

D

10 0 13 15 ns 4.5 Fig.10

D

16 8 20 24 ns 4.5 Fig.11 note:

Dnto PL

t

h

hold time

0 −6 0 0 ns 4.5 Fig.11

Dnto PL

t

h

f

max

hold time

CPUto CPD,CPDto CP

maximum up, down clock

16 7 20 24 ns 4.5 Fig.13

U

20 43 16 13 MHz 4.5 Fig.7

pulse frequency

December 1990 10

CPU=CPD= HIGH

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary

74HC/HCT193

up/down counter

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

Fig.7 Waveforms showing the clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and

= 1.3V; VI= GND to 3 V.

M

the maximum clock pulse frequency.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3V; VI= GND to 3 V.

M

Fig.8 Waveforms showing the clock (CPU,CPD) to terminal count output (TCU, TCD) propagation delays.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3V; VI= GND to 3 V.

M

Fig.9 Waveforms showing the parallel load input (PL) and data (Dn) to Qnoutput propagation delays and

PL removal time to clock input (CPU,CPD).

December 1990 11

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary

74HC/HCT193

up/down counter

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

Fig.10 Waveforms showing the master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU,

= 1.3V; VI= GND to 3 V.

M

CPDremoval time and output transition times.

The shaded areas indicate when the input is permitted to change for predictable output performance.

(1) HC : V

HCT: V

= 50%; VI= GND to VCC.

M

= 1.3V; VI= GND to 3 V.

M

Fig.11 Waveforms showing the data input (Dn) to parallel load input (PL) set-up and hold times.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3V; VI= GND to 3 V.

M

Fig.12 Waveforms showing the data input (Dn), parallel load input (PL) and the master reset input (MR) to the

terminal count outputs (TCU, TCD) propagation delays.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3V; VI= GND to 3 V.

M

Fig.13 Waveforms showing the CPUto CPDor CPDto CPUhold times.

December 1990 12

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary up/down counter

APPLICATION INFORMATION

Fig.14 Cascaded up/down counter with parallel load.

PACKAGE OUTLINES

74HC/HCT193

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.

December 1990 13