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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT190
Presettable synchronous BCD
decade up/down counter
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Presettable synchronous BCD decade
up/down counter
FEATURES
• Synchronous reversible counting
• Asynchronous parallel load
• Count enable control for synchronous expansion
• Single up/down control input
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT190 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT190 are asynchronously presettable
up/down BCD decade counters. They contain four
master/slave flip-flops with internal gating and steering
logic to provide asynchronous preset and synchronous
count-up and count-down operation.
Asynchronous parallel load capability permits the counter
to be preset to any desired number. Information present on
the parallel data inputs (D
and appears on the outputs when the parallel load (PL)
input is LOW. As indicated in the function table, this
operation overrides the counting function.
Counting is inhibited by a HIGH level on the count enable
(CE) input. When CE is LOW internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input. The up/down (U/D) input signal determines
the direction of counting as indicated in the function table.
The CE input may go LOW when the clock is in either
state, however, the LOW-to-HIGH CE transition must
occur only when the clock is HIGH. Also, the U/D input
should be changed only when either CE or CP is HIGH.
to D3) is loaded into the counter
0
74HC/HCT190
Overflow/underflow indications are provided by two types
of outputs, the terminal count (TC) and ripple clock (RC).
The TC output is normally LOW and goes HIGH when a
circuit reaches zero in the count-down mode or reaches “9”
in the count-up-mode. The TC output will remain HIGH
until a state change occurs, either by counting or
presetting, or until U/D is changed. Do not use the TC
output as a clock signal because it is subject to decoding
spikes. The TC signal is used internally to enable the RC
output. When TC is HIGH and CE is LOW, the RC output
follows the clock pulse (CP). This feature simplifies the
design of multistage counters as shown in Figs 5 and 6.
In Fig.5, each RC output is used as the clock input to the
next higher stage. It is only necessary to inhibit the first
stage to prevent counting in all stages, since a HIGH on
CE inhibits theRC output pulse as indicated in the function
table. The timing skew between state changes in the first
and last stages is represented by the cumulative delay of
the clock as it ripples through the preceding stages. This
can be a disadvantage of this configuration in some
applications.
Fig.6 shows a method of causing state changes to occur
simultaneously in all stages. The RC outputs propagate
the carry/borrow signals in ripple fashion and all clock
inputs are driven in parallel. In this configuration the
duration of the clock LOW state must be long enough to
allow the negative-going edge of the carry/borrow signal to
ripple through to the last stage before the clock goes
HIGH. Since the RC output of any package goes HIGH
shortly after its CP input goes HIGH there is no such
restriction on the HIGH-state duration of the clock.
In Fig.7, the configuration shown avoids ripple delays and
their associated restrictions. Combining the TC signals
from all the preceding stages forms the CE input for a
given stage. An enable must be included in each carry
gate in order to inhibit counting. The TC output of a given
stage it not affected by its own CE signal therefore the
simple inhibit scheme of Figs 5 and 6 does not apply.
December 1990 2
Page 3
Philips Semiconductors Product specification
Presettable synchronous BCD decade
up/down counter
QUICK REFERENCE DATA
GND = 0 V; T
SYMBOL PARAMETER CONDITIONS
t
/ t
PHL
PLH
f
max
C
I
C
PD
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
For HCT the condition is VI= GND to VCC− 1.5 V
=25°C; tr=tf= 6 ns
amb
propagation delay CP to Q
n
CL= 15 pF; VCC=5 V2224ns
maximum clock frequency 28 30 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per flip-flop notes 1 and 2 36 38 pF
2
× fi+ ∑ (CL× V
CC
2
× fo) = sum of outputs
CC
2
× fo) where:
CC
CC
74HC/HCT190
TYPICAL
UNIT
HC HCT
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
December 1990 3
Page 4
Philips Semiconductors Product specification
Presettable synchronous BCD decade
up/down counter
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
3, 2, 6, 7 Q
4
5
8 GND ground (0 V)
11
12 TC terminal count output
13
14 CP clock input (LOW-to-HIGH, edge-triggered)
15, 1, 10, 9 D
16 V
to Q
0
3
CE count enable input (active LOW)
U/D up/down input
PL parallel load input (active LOW)
RC ripple clock output (active LOW)
to D
0
3
CC
flip-flop outputs
data inputs
positive supply voltage
74HC/HCT190
Fig.1 Pin configuration.
Fig.3 IEC logic symbol.
December 1990 4
Fig.2 Logic symbol.
Page 5
Philips Semiconductors Product specification
Presettable synchronous BCD decade
74HC/HCT190
up/down counter
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODE
parallel load
count up H L I ↑ X count up
count down H H I ↑ X count down
hold (do nothing) H X H X X no change
PL U/D CE CP D
L
L
INPUTS OUTPUTS
n
X
X
X
X
X
X
L
H
Q
n
L
H
TC AND RC FUNCTION TABLE
INPUTS TERMINAL COUNT STATE OUTPUTS
U/D CE CP Q
HHXHXXH L H
LHXHXXH H H
LL HXXH
LHXLLL L L H
HHXLLL L H H
HL LLL L
Notes
1. H = HIGH voltage level
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
= one LOW level pulse
= TC goes LOW on a LOW-to-HIGH CP transition
0
Q
1
Q
2
Q
3
TC RC
December 1990 5
Page 6
Philips Semiconductors Product specification
Presettable synchronous BCD decade
up/down counter
Fig.5 N-stage ripple counter using ripple clock.
74HC/HCT190
Fig.6 Synchronous n-stage counter using ripple carry/borrow.
Fig.7 Synchronous n-stage counter with parallel gated carry/borrow.
December 1990 6
Page 7
Philips Semiconductors Product specification
Presettable synchronous BCD decade
up/down counter
Sequence
Load (present) to BCD seven;
count up to eight, nine, zero,
one and two;
inhibit;
count down to one, zero, nine,
eight and seven.
74HC/HCT190
Fig.8 Typical load, count and inhibit sequence.
Fig.9 Logic diagram.
December 1990 7
Page 8
Philips Semiconductors Product specification
Presettable synchronous BCD decade
up/down counter
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
/ t
/ t
propagation delay
PLH
CP to Q
propagation delay
PLH
n
CP to TC
t
PHL
/ t
propagation delay
PLH
CP to RC
t
PHL
/ t
propagation delay
PLH
CE to RC
t
PHL
t
PHL
t
PHL
/ t
/ t
/ t
propagation delay
PLH
Dn to Q
propagation delay
PLH
PL to Q
propagation delay
PLH
n
n
U/D to TC
t
PHL
/ t
propagation delay
PLH
U/D to RC
t
THL
t
W
/ t
output transition time 19
TLH
clock pulse width
HIGH or LOW
t
W
parallel load pulse width
LOW
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
+25 −40 TO +85 −40 TO +125
min. typ. max. min. max. min. max.
72
220
26
44
21
37
83
255
30
51
24
43
44
150
16
30
13
26
33
130
12
26
10
22
63
220
23
44
18
37
63
220
23
44
18
37
44
190
16
38
13
32
50
210
18
42
14
36
75
7
15
6
13
155
28
31
10
26
8
100
25
20
9
17
7
T
amb
74HC
195
39
33
125
25
21
(°C)
275
55
47
320
64
54
190
38
33
165
33
28
275
55
47
275
55
47
240
48
41
265
53
45
95
19
16
235
47
40
150
30
26
330
66
56
385
77
65
225
45
38
195
39
33
330
66
56
330
66
56
285
57
48
315
63
54
110
22
19
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
74HC/HCT190
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.10
4.5
6.0
Fig.10
4.5
6.0
Fig.11
4.5
6.0
Fig.11
4.5
6.0
Fig.12
4.5
6.0
Fig.13
4.5
6.0
Fig.14
4.5
6.0
Fig.14
4.5
6.0
Fig.15
4.5
6.0
Fig.10
4.5
6.0
Fig.15
4.5
6.0
December 1990 8
Page 9
Philips Semiconductors Product specification
Presettable synchronous BCD decade
up/down counter
SYMBOL PARAMETER
t
rem
removal time
PL to CP
t
su
set-up time
U/D to CP
t
su
set-up time
Dn to PL
t
su
set-up time
CE to CP
t
h
hold time
U/D to CP
t
h
hold time
Dn to PL
t
h
hold time
CE to CP
f
max
maximum clock pulse
frequency
min. typ. max. min. max. min. max.
35
7
6
205
41
35
100
20
17
140
28
24
0
0
0
0
0
0
0
0
0
3.0
15
18
+25 −40 TO +85 −40 TO +125
8
3
2
61
22
18
19
7
6
39
14
11
−44
−16
−13
−14
−5
−4
−19
−7
−6
8.3
25
30
T
amb
74HC
45
9
8
255
51
43
125
25
21
175
35
30
0
0
0
0
0
0
0
0
0
2.4
12
14
(°C)
55
11
9
310
62
53
150
30
26
210
42
36
0
0
0
0
0
0
0
0
0
2.0
10
12
74HC/HCT190
TEST CONDITIONS
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
V
(V)
4.5
6.0
4.5
6.0
4.5
6.0
4.5
6.0
4.5
6.0
4.5
6.0
4.5
6.0
4.5
6.0
CC
WAVEFORMS
Fig.15
Fig.17
Fig.16
Fig.17
Fig.17
Fig.16
Fig.17
Fig.10
December 1990 9
Page 10
Philips Semiconductors Product specification
Presettable synchronous BCD decade
74HC/HCT190
up/down counter
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
D
n
CP
U/D
CE, PL
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
) for a unit load of 1 is given in the family specifications.
CC
0.5
0.65
1.15
1.5
.
December 1990 10
Page 11
Philips Semiconductors Product specification
Presettable synchronous BCD decade
up/down counter
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
SYMBOL PARAMETER
/ t
t
PHL
PLH
t
/ t
PHL
PLH
t
/ t
PHL
PLH
/ t
t
PHL
PLH
t
/ t
PHL
PLH
t
/ t
PHL
PLH
t
/ t
PHL
PLH
t
/ t
PHL
PLH
t
/ t
THL
TLH
= 6 ns; CL= 50 pF
r=tf
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
propagation delay
CP to Q
n
propagation delay
28 48 60 72 ns 4.5 Fig.10
34 58 73 87 ns 4.5 Fig.10
CP to TC
propagation delay
20 35 44 53 ns 4.5 Fig.11
CP to RC
propagation delay
18 33 41 50 ns 4.5 Fig.11
CE to RC
propagation delay
Dn to Q
n
propagation delay
PL to Q
n
propagation delay
24 44 55 66 ns 4.5 Fig.12
29 49 61 74 ns 4.5 Fig.13
24 45 56 68 ns 4.5 Fig.14
U/D to TC
propagation delay
26 45 56 68 ns 4.5 Fig.14
U/D to RC
output transition time 7 15 19 22 ns 4.5 Fig.15
T
amb
74HCT
(°C)
74HC/HCT190
TEST CONDITIONS
UNIT
V
CC
(V)
WAVEFORMS
t
W
t
W
t
rem
t
su
t
su
t
su
t
h
t
h
t
h
f
max
clock pulse width
HIGH or LOW
parallel load pulse width
LOW
removal time
PL to CP
set-up time
U/D to CP
set-up time
Dn to PL
set-up time
CE to CP
hold time
U/D to CP
hold time
Dn to PL
hold time
CE to CP
maximum clock pulse
frequency
25 10 31 38 ns 4.5 Fig.10
22 12 28 33 ns 4.5 Fig.15
7 1 9 11 ns 4.5 Fig.15
42 25 53 63 ns 4.5 Fig.17
20 10 25 30 ns 4.5 Fig.16
31 18 39 47 ns 4.5 Fig.17
0 −18 0 0 ns 4.5 Fig.17
0 −6 0 0 ns 4.5 Fig.16
0 −10 0 0 ns 4.5 Fig.17
16 27 13 11 MHz 4.5 Fig.10
December 1990 11
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Philips Semiconductors Product specification
Presettable synchronous BCD decade
up/down counter
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
Fig.10 Waveforms showing the clock (CP) to
= 1.3 V; VI= GND to 3 V.
M
output (Qn) propagation delays, the clock
pulse width and the maximum clock pulse
frequency.
74HC/HCT190
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
Fig.11 Waveforms showing the clock and count
= 1.3 V; VI= GND to 3 V.
M
enable inputs (CP, CE) to ripple clock
output (RC) propagation delays.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.12 Waveforms showing the input (Dn) to output
(Qn) propagation delays.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.14 Waveforms showing the up/down count
input (U/D) to terminal count and ripple
clock output (TC, RC) propagation delays.
December 1990 12
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.13 Waveforms showing the input (PL) to output
(Qn) propagation delays.
(1) HC :
= 50%;
V
M
= GND to
V
I
.
V
CC
HCT :
VM= 1.3 V;
= GND to
V
I
3V.
Fig.15 Waveforms showing the parallel load input
(PL) pulse width, removal time to clock (CP)
and the output (Qn) transition times.
Page 13
Philips Semiconductors Product specification
Presettable synchronous BCD decade
up/down counter
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V
HCT : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
74HC/HCT190
Fig.16 Waveforms showing the set-up and hold times from the parallel load input (PL) to the data input (Dn).
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V
HCT : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the
clock (CP).
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 13
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