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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT166
8-bit parallel-in/serial-out shift
register
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
FEATURES
• Synchronous parallel-to-serial applications
• Synchronous serial data input for easy expansion
• Clock enable for “do nothing” mode
• Asynchronous master reset
• For asynchronous parallel data load see “165”
• Output capability: standard
• ICC category: MSI
an active LOW parallel enable (
LOW one set-up time prior to the LOW-to-HIGH clock
transition, parallel data is entered into the register. When
PE is HIGH, data is entered into the internal bit position Q
from serial data input (Ds), and the remaining bits are
shifted one place to the right (Q0→ Q1→ Q2, etc.) with
each positive-going clock transition.
This feature allows parallel-to-serial converter expansion
by tying the Q7 output to the Ds input of the succeeding
stage.
The clock input is a gated-OR structure which allows one
GENERAL DESCRIPTION
The 74HC/HCT166 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT166 are 8-bit shift registers which have a
fully synchronous serial or parallel data entry selected by
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of inputCE should only take place
while CP is HIGH for predictable operation. A LOW on the
master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all bit positions
to a LOW state.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
f
max
C
C
I
PD
/ t
PLH
propagation delay
CP to Q
MR to Q
7
7
CL= 15 pF; VCC=5 V
maximum clock frequency 63 50 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 41 41 pF
PE) input. When PE is
TYPICAL
UNIT
HC HCT
15
14
20
19
ns
ns
0
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
December 1990 2
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1D
2, 3, 4, 5, 10, 11, 12, 14 D
6
s
to D
0
7
CE clock enable input (active LOW)
7 CP clock input (LOW-to-HIGH edge-triggered)
8 GND ground (0 V)
9
13 Q
15
16 V
MR asynchronous master reset (active LOW)
7
PE parallel enable input (active LOW)
CC
serial data input
parallel data inputs
serial output from the last stage
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODES
INPUTS Qn REGISTER OUTPUT
parallel load
serial shift
PE CE CP D
I
I
h
h
I
I
I
I
↑
↑
↑
↑
S
X
X
I
h
hold “do nothing” X h X X X - X q
D0-D
I- I
h - h
X - X
X-X
L
H
L
H
Q
0
L - L
H - H
q
0
q0- q
0
q1 - q
7
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
Q1-Q
- q
6
Q
7
L
H
5
5
6
q
6
q
6
q
7
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
Fig.5 Logic diagram.
Fig.6 Typical clear, shift, load, inhibit, and shift sequences.
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
THL
t
W
/ t
/ t
propagation delay
PLH
CP to Q
7
propagation delay
MR to Q
output transition time 19
TLH
7
clock pulse width
HIGH or LOW
t
W
master reset pulse width
LOW
t
rem
removal time
MR to CP
t
su
set-up time
Dn, CE to CP
t
su
set-up time
PE to CP
t
h
hold time
Dn, CE to CP
t
h
hold time
PE to CP
f
max
maximum clock pulse
frequency
(°C)
T
amb
74HC
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
50
80
16
14
100
20
17
0
0
0
80
16
14
100
20
17
2
2
2
0
0
0
6.0
30
35
18
14
47
17
14
7
6
17
6
5
25
9
7
−19
−7
−6
14
5
4
33
12
10
−8
−3
−2
−28
−10
−8
19
57
68
150
30
26
160
32
27
75
15
13
100
20
17
125
25
21
0
0
0
100
20
17
125
25
21
2
2
2
0
0
0
4.8
24
28
190
38
33
200
40
34
95
19
16
225
45
38
240
48
41
110
22
19
120
24
20
150
30
26
0
0
0
120
24
20
150
30
26
2
2
2
0
0
0
4.0
20
24
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.9
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.9
4.5
6.0
Fig.7
4.5
6.0
December 1990 6
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
D0 to D
D
s
CP
CE
MR
PE
0.35
7
0.35
0.80
0.80
0.40
0.60
December 1990 7
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
THL
t
W
/ t
/ t
propagation delay
PLH
CP to Q
7
propagation delay
MR to Q
output transition time 7 15 19 22 ns 4.5 Fig.7
TLH
7
clock pulse width
HIGH or LOW
t
W
master reset pulse width
LOW
t
rem
removal time
MR to CP
t
su
set-up time
Dn, CE to CP
t
su
set-up time
PE to CP
t
h
t
h
f
max
hold time
Dn, CE to CP
hold time
PE to CP
maximum clock pulse
width
T
amb
(°C)
TEST CONDITIONS
74HCT
+25 −40 to +85 −40 to +125
UNIT
WAVEFORMS
V
CC
(V)
min. typ. max. min. max. min. max.
23 40 50 60 ns 4.5 Fig.7
22 40 50 60 ns 4.5 Fig.8
20 9 25 30 ns 4.5 Fig.7
25 11 31 38 ns 4.5 Fig.8
0 −7 0 0 ns 4.5 Fig.8
16 8 20 24 ns 4.5 Fig.9
30 15 38 45 ns 4.5 Fig.8
0 −3 0 0 ns 4.5 Fig.9
0 −13 0 0 ns 4.5 Fig.9
25 45 20 17 MHz 4.5 Fig.7
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
AC WAVEFORMS
The changing to output assumes internal Q6 opposite state from Q7.
The number of clock pulses required between the t
measurements can be determined from the function table.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3V; VI= GND to 3V.
HCT: V
M
Fig.7 Waveforms showing the clock (CP) to output (Q7) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
PLH
and t
PHL
The number of clock pulses required between the t
measurements can be determined from the function table.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3V; VI= GND to 3V.
HCT: V
M
PLH
and t
PHL
Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7) propagation delay
and the master reset to clock (CP) removal time.
December 1990 9
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
The number of clock pulses required between the t
measurements can be determined from the function table.
CE may change only from HIGH-to-LOW while CP is LOW.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
(1) HC : V
= 50%; VI= GND to VCC.
M
= 1.3V; VI= GND to 3V.
HCT: V
M
PLH
and t
PHL
Fig.9 Waveforms showing the set-up and hold times from the serial data input (Ds), the data inputs (Dn), the
clock enable input (LOW CE), the clock enable input CE and the parallel enable input to the clock (CP).
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 10
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