Datasheet 74 hct164 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT164

8-bit serial-in/parallel-out shift
register

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

8-bit serial-in/parallel-out shift register 74HC/HCT164

FEATURES

• Gated serial data inputs

• Asynchronous master reset

• Output capability: standard

• ICC category: MSI

Data is entered serially through one of two inputs (D
Dsb); either input can be used as an active HIGH enable for
data entry through the other input.
Both inputs must be connected together or an unused
input must be tied HIGH.

Data shifts one place to the right on each LOW-to-HIGH
transition of the clock (CP) input and enters into Q0, which

GENERAL DESCRIPTION

The 74HC/HCT164 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

is the logical AND of the two data inputs (Dsa,Dsb) that
existed one set-up time prior to the rising clock edge.

A LOW level on the master reset (MR) input overrides all
other inputs and clears the register asynchronously,
forcing all outputs LOW.

The 74HC/HCT164 are 8-bit edge-triggered shift registers
with serial data entry and an output from each of the eight
stages.

QUICK REFERENCE DATA

GND = 0 V; T

= 25 °C; tr= tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

f

max

C
C

I
PD

/ t

PLH

propagation delay

CP to Q
MR to Q

n

n

CL= 15 pF; VCC= 5 V

maximum clock frequency 78 61 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per

notes 1 and 2

package

TYPICAL

HC HCT

12
11

14
16

ns
ns

40 40 pF

sa

UNIT

or

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD= CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

December 1990 2

.

Philips Semiconductors Product specification

8-bit serial-in/parallel-out shift register 74HC/HCT164

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 2 D
3, 4, 5, 6, 10, 11, 12, 13 Q

sa,Dsb

to Q

0

7

7 GND ground (0 V)
8 CP clock input (LOW-to-HIGH, edge-triggered)
9
14 V

MR master reset input (active LOW)

CC

data inputs
outputs

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol.

December 1990 3

Fig.3 IEC logic symbol.

Philips Semiconductors Product specification

8-bit serial-in/parallel-out shift register 74HC/HCT164

Fig.4 Functional diagram.

APPLICATIONS

• Serial data transfer

FUNCTION TABLE

INPUTS OUTPUTS

OPERATING MODES

MR CP D

sa

D

sb

Q

Q1− Q

0

reset (clear) L X X X L L − L

shift

H
H
H
H

↑
↑
↑
↑

l
l
h
h

l
h
l
h

L
L
L
H

q

0

q0− q
q0− q
q0− q

Note

1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the

LOW-to-HIGH clock transition

↑ = LOW-to-HIGH clock transition

− q

7

6
6
6
6

Fig.5 Logic diagram.

December 1990 4

Philips Semiconductors Product specification

8-bit serial-in/parallel-out shift register 74HC/HCT164

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard
ICCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= tf= 6 ns; CL= 50 pF

r

SYMBOL PARAMETER

min. typ. max. min. max. min. max.

t

PHL

t

PHL

t

THL

/ t

/ t

propagation delay

PLH

CP to Q

propagation delay

MR to Q

output transition

TLH

n

n

time

t

W

clock pulse width

HIGH or LOW

80
16
14

t

W

master reset pulse

width; LOW

60
12
10

t

rem

removal time

MR to CP

60
12
10

t

su

set-up time

Dsa, Dsbto CP

60
12
10

t

h

hold time

Dsa,Dsbto CP

4
4
4

f

max

maximum clock

pulse frequency630

35

(°C)

T

amb

74HC

+25 −40 to +85 −40 to +125

41
15
12

39
14
11

19
7
6

14
5
4

17
6
5

17
6
5

8
3
2

−6

−2

−2

23
71
85

170
34
29

140
28
24

75
15
13

100
20
17

75
15
13

75
15
13

75
15
13

4
4
4

5
24
28

215
43
37

175
35
30

95
19
16

255
51
43

210
42
36

110
22
19

120
24
20

90
18
15

90
18
15

90
18
15

4
4
4

4
20
24

.

UNIT

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

MHz 2.0

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.6

4.5

6.0
Fig.6

4.5

6.0
Fig.6

4.5

6.0
Fig.6

4.5

6.0
Fig.6

4.5

6.0
Fig.6

4.5

6.0
Fig.6

4.5

6.0
Fig.6

4.5

6.0
Fig.6

4.5

6.0

December 1990 5

Philips Semiconductors Product specification

8-bit serial-in/parallel-out shift register 74HC/HCT164

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: standard
ICCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I

) for a unit load of 1 is given in the family specifications.

CC

To determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

Dsa,D
CP
MR

sb

0.25

0.60

0.90

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= tf= 6 ns; CL= 50 pF

r

T

amb

(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

+25 −40 to +85 −40 to +125

UNIT

V

(V)

min. typ. max. min. max. min. max.

t

PHL

t

PHL

t

THL

/ t

/ t

propagation delay

PLH

CP to Q

n

propagation delay

MR to Q

output transition time 7 15 19 22 ns 4.5 Fig.6

TLH

n

17 36 45 54 ns 4.5 Fig.6

19 38 48 57 ns 4.5 Fig.6

WAVEFORMS

CC

t

W

clock pulse width

18 7 23 27 ns 4.5 Fig.6

HIGH or LOW

t

W

master reset pulse

18 10 23 27 ns 4.5 Fig.6

width; LOW

t

rem

removal time

16 7 20 24 ns 4.5 Fig.6

MR to CP

t

su

set-up time

12 6 15 18 ns 4.5 Fig.6

Dsa,Dsbto CP

t

h

hold time

4 −2 4 4 ns 4.5 Fig.6

Dsa,Dsbto CP

f

max

maximum clock pulse

27 55 22 18 MHz 4.5 Fig.6

frequency

December 1990 6

Philips Semiconductors Product specification

8-bit serial-in/parallel-out shift register 74HC/HCT164

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

HCT : V

= 1.3 V; VI= GND to 3 V.

M

Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output

transition times and the maximum clock frequency.

(1) HC : VM= 50%; VI= GND to VCC.

HCT : V

= 1.3 V; VI= GND to 3 V.

M

Fig.7 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation

delays and the master reset to clock (CP) removal time.

(1) HC : VM= 50%; VI= GND to VCC.

HCT : V

= 1.3 V; VI= GND to 3 V.

M

Fig.8 Waveforms showing the data set-up and hold times for Dninputs.

December 1990 7

Philips Semiconductors Product specification

8-bit serial-in/parallel-out shift register 74HC/HCT164

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.

December 1990 8