Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT162
Presettable synchronous BCD
decade counter; synchronous reset
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Presettable synchronous BCD decade
counter; synchronous reset
FEATURES
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive-edge triggered clock
• Synchronous reset
• Output capability: standard
• ICCcategory: MSI
GENERAL DESCRIPTION
The 74HC/HCT162 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT162 are synchronous presettable decade
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the
data at the data inputs (D0to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
to Q3) of the counters may be preset to a
0
74HC/HCT162
that the set-up and hold time requirements forPE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
For the “162” the clear function is synchronous.
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q0to Q3) to LOW level after the
next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for
MR are met). This action occurs regardless of the levels at
PE, CET and CEP inputs.
This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND
gate.
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
f
max
--------------------------------------------------------------------------------------------------------
=
t
Pmax()
CP to TC()t
1
(CEP to CP)+
SU
QUICK REFERENCE DATA
GND = 0 V; T
= 25 °C; tr= tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
t
PLH
f
max
propagation delay
CP to Q
n
CP to TC
CET to TC
propagation delay
CP to Q
n
CP to TC
CET to TC
maximum clock
CL= 15 pF;
VCC=5V 19
21
11
19
21
11
63 32 MHz
frequency
C
I
C
PD
input capacitance 3.5 3.5 pF
power dissipation
notes 1 and 2 37 37 pF
capacitance per package
December 1990 2
TYPICAL
HC HCT
20
26
15
20
19
10
UNIT
ns
ns
ns
ns
ns
ns
Notes
1. CPDis used to determine the
dynamic power dissipation
(PDin µW):
CC
2
CC
× fo)
2
× fi+
PD= CPD× V
∑ (CL× V
where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of
CC
outputs
CL= output load capacitance in
pF
VCC= supply voltage in V
2. For HC the condition is
VI= GND to V
CC
For HCT the condition is
VI= GND to VCC− 1.5 V
Page 3
Philips Semiconductors Product specification
Presettable synchronous BCD decade
counter; synchronous reset
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
2 CP clock input (LOW-to-HIGH, edge-triggered)
3, 4, 5, 6 D
7 CEP count enable input
8 GND ground (0 V)
9
10 CET count enable carry input
14, 13, 12, 11 Q
15 TC terminal count output
16 V
MR synchronous master reset (active LOW)
to D
0
3
PE parallel enable input (active LOW)
to Q
0
3
CC
data inputs
flip-flop outputs
positive supply voltage
.
74HC/HCT162
Fig.1 Pin configuration.
December 1990 3
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
Page 4
Philips Semiconductors Product specification
Presettable synchronous BCD decade
counter; synchronous reset
Fig.4 Functional diagram.
74HC/HCT162
FUNCTION TABLE
INPUTS OUTPUTS
OPERATING MODE
MR CP CEP CET PE D
n
Q
n
TC
reset (clear) I ↑ XXXXL L
parallel load h
h
count h ↑ h h h X count
hold
(do nothing)
h
h
↑
↑
X
X
X
X
I
X
X
X
X
I
I
I
h
h
I
h
X
X
L
H
q
n
q
n
L
(1)
(1)
(1)
L
Notes
1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
December 1990 4
Page 5
Philips Semiconductors Product specification
Presettable synchronous BCD decade
counter; synchronous reset
Fig.5 State diagram.
74HC/HCT162
Fig.6 Typical timing sequence: reset outputs to zero; preset to BCD seven; count to eight, nine, zero, one, two
and three; inhibit.
December 1990 5
Page 6
Philips Semiconductors Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
Fig.7 Logic diagram.
December 1990 6
Page 7
Philips Semiconductors Product specification
Presettable synchronous BCD decade
counter; synchronous reset
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
Output capability: standard
ICCcategory: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= tf= 6 ns; CL= 50 pF
r
SYMBOL PARAMETER
t
PHL
t
PHL
/ t
/ t
propagation delay
PLH
CP to Q
propagation delay
PLH
n
CP to TC
t
PHL
/ t
propagation delay
PLH
CET to TC
t
THL
/ t
output transition
TLH
time
t
W
clock pulse width
HIGH or LOW
t
su
set-up time
MR, Dnto CP
t
su
set-up time
PE to CP
t
su
set-up time
CEP, CET to CP
t
h
hold time
Dn, PE, CEP,
CET, MR to CP
f
max
maximum clock
pulse
frequency
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
58
190
21
38
17
32
69
215
25
43
20
37
39
150
14
30
11
26
19
75
7
15
6
13
80
22
16
8
14
6
100
28
20
10
17
8
135
39
27
14
23
11
200
69
40
25
34
20
0
−17
0
−6
0
−5
6.0
19
30
57
35
68
T
amb
74HC
100
20
17
125
25
21
170
34
29
250
50
43
0
0
0
4.8
24
28
(°C)
240
48
41
270
54
46
190
38
33
95
19
16
120
24
20
150
30
26
205
41
35
300
60
51
0
0
0
4.0
20
24
285
57
48
325
65
55
225
45
38
110
22
19
74HC/HCT162
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.9
4.5
6.0
Figs 8 and 9
4.5
6.0
Fig.8
4.5
6.0
Figs 9 and 11
4.5
6.0
Fig.9
4.5
6.0
Fig.12
4.5
6.0
Figs 9, 11 and
4.5
12
6.0
Fig.8
4.5
6.0
December 1990 7
Page 8
Philips Semiconductors Product specification
Presettable synchronous BCD decade
74HC/HCT162
counter; synchronous reset
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: standard
ICCcategory: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
To determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
MR 0.95
CP 0.80
CEP 0.25
D
n
CET 1.50
PE 0.30
0.25
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
) for a unit load of 1 is given in the family specifications.
CC
.
December 1990 8
Page 9
Philips Semiconductors Product specification
Presettable synchronous BCD decade
counter; synchronous reset
AC CHARACTERISTICS FOR HCT
GND = 0 V; t
SYMBOL PARAMETER
/ t
t
PHL
PLH
t
PHL
t
PLH
t
PHL
t
PLH
/ t
t
THL
TLH
= tf= 6 ns; CL= 50 pF
r
+25 −40 to +85 −40
min. typ. max. min. max. min. max.
propagation delay
CP to Q
n
propagation delay
24 43 54 65 ns 4.5 Fig.8
30 51 64 77 ns 4.5 Fig.8
CP to TC
propagation delay
22 45 56 68 ns 4.5 Fig.8
CP to TC
propagation delay
18 35 44 53 ns 4.5 Fig.9
CET to TC
propagation delay
12 24 30 36 ns 4.5 Fig.9
CET to TC
output transition time 7 15 19 22 ns 4.5 Figs 8 and 9
T
amb
74HCT
(°C)
to +125
UNIT
74HC/HCT162
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
t
W
t
su
t
su
t
su
t
su
t
h
f
max
clock pulse width
HIGH or LOW
set-up time
Dnto CP
set-up time
PE to CP
set-up time
CEP, CET to CP
set-up time
MR to CP
hold time
Dn, PE, CEP,
CET, MR to CP
maximum clock
pulse frequency
16 7 20 24 ns 4.5 Fig.8
20 9 25 30 ns 4.5 Fig.9
35 16 44 53 ns 4.5 Fig.9
40 23 50 60 ns 4.5 Fig.12
20 12 25 30 ns 4.5 Fig.11
0 −10 0 0 ns 4.5 Figs 9, 11 and 12
17 29 14 11 MHz 4.5 Fig.8
December 1990 9
Page 10
Philips Semiconductors Product specification
Presettable synchronous BCD decade
74HC/HCT162
counter; synchronous reset
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
Fig.8 Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the
= 1.3 V; VI= GND to 3 V.
M
output transition times and the maximum clock frequency.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.9 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
HCT : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
Fig.10 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input (PE).
December 1990 10
Page 11
Philips Semiconductors Product specification
Presettable synchronous BCD decade
counter; synchronous reset
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
HCT : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
Fig.11 Waveforms showing the MR set-up and hold times.
74HC/HCT162
The shaded areas indicate when the input is permitted
to change for predictable output performance.
(1) HC : V
HCT : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
Fig.12 Waveforms showing the CEP and CET set-up and hold times.
APPLICATION INFORMATION
The HC/HCT162 facilitate designing counters of any modulus with minimal external logic.
The output is glitch-free due to the synchronous reset.
Fig.13 Modulo-5 counter.
PACKAGE OUTLINES
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
See
.
December 1990 11
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