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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT161
Presettable synchronous 4-bit
binary counter; asynchronous reset
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
FEATURES
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive-edge triggered clock
• Asynchronous reset
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT161 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT161 are synchronous presettable binary
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q
HIGH or LOW level. A LOW level at the parallel enable
to Q3) of the counters may be preset to a
0
74HC/HCT161
input (PE) disables the counting action and causes the
data at the data inputs (D0 to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements forPE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q0 to Q3) to LOW level regardless
of the levels at CP, PE, CET and CEP inputs (thus
providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
f
max
---------------------------------------------------------------------------------------------------
=
t
(CP to TC) t+SU(CEP to CP)
P(max)
1
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
/ t
propagation delay
PLH
CP to Q
CL= 15 pF;
n
VCC=5 V 19
CP to TC
MR to Q
n
MR to TC
CET to TC
f
max
C
C
I
PD
maximum clock frequency 44 45 MHz
input capacitance 3.5 3.5 pF
power dissipation
notes 1 and 2 33 35 pF
capacitance per package
TYPICAL
HC HCT
20
21
20
20
10
24
25
26
14
UNIT
ns
ns
ns
ns
ns
Notes
1. CPD is used to determine the
dynamic power dissipation
(PD in µW):
CC
CC
2
2
× fi+
× fo)
PD=CPD× V
∑ (CL× V
where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of
CC
outputs
CL= output load capacitance in
pF
VCC= supply voltage in V
2. For HC the condition is
VI= GND to V
CC
For HCT the condition is
VI= GND to VCC− 1.5 V
December 1990 2
Page 3
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
2 CP clock input (LOW-to-HIGH, edge-triggered)
3, 4, 5, 6 D
7 CEP count enable input
8 GND ground (0 V)
9
10 CET count enable carry input
14, 13, 12, 11 Q
15 TC terminal count output
16 V
MR asynchronous master reset (active LOW)
to D
0
3
PE parallel enable input (active LOW)
to Q
0
3
CC
data inputs
flip-flop outputs
positive supply voltage
.
74HC/HCT161
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
Page 4
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
Fig.4 Functional diagram.
74HC/HCT161
FUNCTION TABLE
INPUTS OUTPUTS
OPERATING MODE
MR CP CEP CET PE D
n
Q
n
reset (clear) L X X X X X L L
parallel load H
H
↑
↑
X
X
X
X
I
I
I
h
L
H
count H ↑ h h h X count
hold
(do nothing)
H
H
X
X
I
X
X
I
h
h
X
X
q
n
q
n
Note
1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
TC
L
(1)
(1)
(1)
L
December 1990 4
Page 5
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
Fig.5 State diagram.
Fig.6 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen,
zero, one and two; inhibit.
December 1990 5
Page 6
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
Fig.7 Logic diagram.
December 1990 6
Page 7
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
/ t
/ t
propagation delay
PLH
CP to Q
propagation delay
PLH
n
CP to TC
t
PHL
t
PHL
propagation delay
MR to Q
n
propagation delay
MR to TC
t
PHL
/ t
propagation delay
PLH
CET to TC
t
THL
t
W
/ t
output transition time 19
TLH
clock pulse width
HIGH or LOW
t
W
master reset pulse
width; LOW
t
rem
removal time
MR to CP
t
su
set-up time
Dn to CP
t
su
set-up time
PE to CP
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
min. typ. max. min. max. min. max.
61
190
22
38
18
32
69
215
25
43
20
37
63
210
23
42
18
36
63
220
23
44
18
37
33
150
12
30
10
26
75
7
15
6
13
80
22
16
8
14
6
80
19
16
7
14
6
100
19
20
7
17
6
80
25
16
9
14
7
100
30
20
11
17
9
T
amb
74HC
100
20
17
100
20
17
125
25
21
100
20
17
125
25
21
(°C)
240
48
41
270
54
46
265
53
45
275
55
47
190
38
33
95
19
16
120
24
20
120
24
20
150
30
26
120
24
20
150
30
26
285
57
48
325
65
55
315
63
54
330
66
56
225
45
38
110
22
19
74HC/HCT161
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.9
4.5
6.0
Fig.9
4.5
6.0
Fig.10
4.5
6.0
Figs 8 and 10
4.5
6.0
Fig.8
4.5
6.0
Fig.9
4.5
6.0
Fig.9
4.5
6.0
Fig.11
4.5
6.0
Fig.11
4.5
6.0
December 1990 7
Page 8
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
SYMBOL PARAMETER
min. typ. max. min. max. min. max.
t
su
t
h
f
max
set-up time
CEP, CET to CP
hold time
Dn, PE, CEP,
CET to CP
maximum clock pulse
frequency
170
34
29
0
0
0
4.6
23
27
47
17
14
−14
−5
−4
13
40
48
T
amb
74HC
215
43
37
0
0
0
3.6
18
21
(°C)
255
51
43
0
0
0
3.0
15
18
74HC/HCT161
TEST CONDITIONS
UNIT
ns 2.0
ns 2.0
MHz 2.0
V
(V)
4.5
6.0
4.5
6.0
4.5
6.0
CC
WAVEFORMS+25 −40 to +85 −40 to +125
Fig.12
Figs 11 and 12
Fig.8
December 1990 8
Page 9
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
74HC/HCT161
counter; asynchronous reset
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
MR 0.95
CP 1.10
CEP 0.25
D
n
0.25
CET 0.75
PE 0.30
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
) for a unit load of 1 is given in the family specifications.
CC
.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
min. typ. max. min. max. min. max.
t
PHL
t
PHL
/ t
/ t
propagation delay
PLH
CP to Q
propagation delay
PLH
n
CP to TC
t
PHL
t
PHL
propagation delay
MR to Q
n
propagation delay
MR to TC
t
PHL
/ t
propagation delay
PLH
CET to TC
t
THL
t
W
/ t
output transition time 7 15 19 22 ns 4.5 Figs 8 and 10
TLH
clock pulse width
16 7 20 24 ns 4.5 Fig.8
HIGH or LOW
t
W
master reset pulse
20 10 25 30 ns 4.5 Fig.9
width; LOW
t
rem
removal time
20 6 25 30 ns 4.5 Fig.9
MR to CP
T
amb
(°C)
TEST CONDITIONS
74HCT
+25 −40 to +85 −40 to +125
UNIT
V
CC
(V)
WAVEFORMS
23 43 54 65 ns 4.5 Fig.8
28 48 60 72 ns 4.5 Fig.8
29 46 58 69 ns 4.5 Fig.9
30 51 64 77 ns 4.5 Fig.9
17 35 44 53 ns 4.5 Fig.10
December 1990 9
Page 10
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
SYMBOL PARAMETER
t
su
set-up time
Dn to CP
t
su
set-up time
PE to CP
t
su
set-up time
CEP, CET to CP
t
h
hold time
Dn, PE, CEP,
CET to CP
f
max
maximum clock pulse
frequency
min. typ. max. min. max. min. max.
18 8 23 27 ns 4.5 Fig.11
30 17 38 45 ns 4.5 Fig.11
40 17 50 60 ns 4.5 Fig.12
0 −7 0 0 ns 4.5 Figs 11 and 12
23 41 18 15 MHz 4.5 Fig.8
+25 −40 to +85 −40 to +125
T
amb
74HCT
(°C)
74HC/HCT161
TEST CONDITIONS
UNIT
V
CC
(V)
WAVEFORMS
December 1990 10
Page 11
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
74HC/HCT161
counter; asynchronous reset
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
Fig.8 Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the
= 1.3 V; VI= GND to 3 V.
HCT: V
M
output transition times and the maximum clock frequency.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.9 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn, TC) propagation
delays and the master reset to clock (CP) removal time.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.10 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times.
December 1990 11
Page 12
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
74HC/HCT161
counter; asynchronous reset
The shaded areas indicate when the input is permitted to change
for predictable output performance.
(1) HC : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.11 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input PE.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.12 Waveforms showing the CEP and CET set-up and hold times.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 12
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