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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT157
Quad 2-input multiplexer
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Quad 2-input multiplexer 74HC/HCT157
FEATURES
• Non-inverting data path
• Output capability: standard
• ICCcategory: MSI
GENERAL DESCRIPTION
The 74HC/HCT157 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT157 are quad 2-input multiplexers which
select 4 bits of data from two sources under the control of
a common data select input (S). The four outputs present
the selected data in the true (non-inverted) form. The
enable input (
E) is active LOW. When E is HIGH, all of the
outputs (1Y to 4Y) are forced LOW regardless of all other
input conditions.
QUICK REFERENCE DATA
GND = 0 V; T
= 25 °C; tr= tf= 6 ns
amb
Moving the data from two groups of registers to four
common output buses is a common use of the “157”. The
state of the common data select input (S) determines the
particular register from which the data comes. It can also
be used as function generator.
The device is useful for implementing highly irregular logic
by generating any four of the 16 different functions of two
variables with one variable common.
The “157” is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to S.
The logic equations are:
1Y = E.(1l1.S + 1l0.S)
2Y = E.(2l1.S + 2l0.S)
3Y = E.(3l1.S + 3l0.S)
4Y = E.(4l1.S + 4l0.S)
The “157” is identical to the “158” but has non-inverting
(true) outputs.
SYMBOL PARAMETER CONDITIONS
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC= 5 V
nI
, nI1to nY 11 13 ns
0
E to nY 11 12 ns
S to nY 12 19 ns
C
I
C
PD
input capacitance 3.5 3.5 pF
power dissipation capacitance per multiplexer notes 1 and 2 70 70 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW):
PD
PD= CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
TYPICAL
UNIT
HC HCT
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
December 1990 2
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Philips Semiconductors Product specification
Quad 2-input multiplexer 74HC/HCT157
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1 S common data select input
2, 5, 11, 14 1I
3, 6, 10, 13 1I
4, 7, 9, 12 1Y to 4Y multiplexer outputs
8 GND ground (0 V)
15
16 V
0
1
to 4I
to 4I
0
1
data inputs from source 0
data inputs from source 1
E enable input (active LOW)
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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Philips Semiconductors Product specification
Quad 2-input multiplexer 74HC/HCT157
FUNCTION TABLE
INPUTS OUTPUT
Fig.4 Functional diagram.
ESnI
HXXX L
L
L
L
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
L
L
H
H
0nI1
L
H
X
X
X
X
L
H
nY
L
H
L
H
Fig.5 Logic diagram.
December 1990 4
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Philips Semiconductors Product specification
Quad 2-input multiplexer 74HC/HCT157
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICCcategory: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= tf= 6 ns; CL= 50 pF
r
SYMBOL PARAMETER
min. typ. max. min. max. min. max.
t
PHL
/ t
propagation delay
PLH
nI0to nY;
nI1to nY
t
PHL
/ t
propagation delay
PLH
E to nY
t
PHL
/ t
propagation delay
PLH
S to nY
t
THL
/ t
output transition
TLH
time
T
(°C)
amb
74HC
+25 −40 to +85 −40 to +125
36
13
10
39
14
11
41
15
12
19
7
6
125
25
21
115
23
20
125
25
21
75
15
13
155
31
26
145
29
25
155
31
26
95
19
16
190
38
32
175
35
30
190
38
32
110
22
19
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
V
CC
WAVEFORMS
(V)
Fig.7
4.5
6.0
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Fig.6 and Fig.7
4.5
6.0
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Philips Semiconductors Product specification
Quad 2-input multiplexer 74HC/HCT157
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
nI
0
nI
1
E
S
1.00
1.00
0.60
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
T
amb
(°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
t
PHL
/ t
propagation delay
PLH
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
16 27 34 41 ns 4.5 Fig.7
UNIT
V
(V)
nI0to nY;
nI1to nY
t
PHL
/ t
propagation delay
PLH
15 26 33 39 ns 4.5 Fig.6
E to nY
t
PHL
/ t
propagation delay
PLH
22 37 46 56 ns 4.5 Fig.7
S to nY
t
THL
/ t
output transition
TLH
7 15 19 22 ns 4.5 Fig.6 and Fig.7
time
WAVEFORMS
CC
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Philips Semiconductors Product specification
Quad 2-input multiplexer 74HC/HCT157
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.6 Waveforms showing the enable input (E) to output (nY) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.7 Waveforms showing the data inputs (nIn) and common data select input (S) to output (nY) propagation
delays.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 7
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