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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT154
4-to-16 line decoder/demultiplexer
Product specification
File under Integrated Circuits, IC06
September 1993
Page 2
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
FEATURES
• 16-line demultiplexing capability
• Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs
• 2-input enable gate for strobing or expansion
• Output capability: standard
• ICC category: MSI
The 74HC/HCT154 decoders accept four active HIGH
binary address inputs and provide 16 mutually exclusive
active LOW outputs.
The 2-input enable gate can be used to strobe the decoder
to eliminate the normal decoding “glitches” on the outputs,
or it can be used for the expansion of the decoder.
The enable gate has two AND’ed inputs which must be
LOW to enable the outputs.
The “154” can be used as a 1-to-16 demultiplexer by using
GENERAL DESCRIPTION
The 74HC/HCT154 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
one of the enable inputs as the multiplexed data input.
When the other enable is LOW, the addressed output will
follow the state of the applied data.
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/ tPLH
C
I
C
PD
propagation delay An, En to Y
n
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 60 60 pF
CL= 15 pF; VCC=5 V 11 13 ns
TYPICAL
UNIT
HC HCT
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
September 1993 2
Page 3
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17
18, 19
12 GND ground (0 V)
23, 22, 21, 20 A
24 V
Y0 to Y
E0, E
to A
0
CC
15
1
3
outputs (active LOW)
enable inputs (active LOW)
address inputs
positive supply voltage
(a) (b)
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
September 1993 3
Page 4
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
FUNCTION TABLE
INPUTS OUTPUTS
E0E1A0A1A2A3Y0Y1Y2Y3Y4Y5Y6Y7Y8Y9Y10Y11Y12Y13Y14Y
H
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
15
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Fig.5 Logic diagram.
September 1993 4
Page 5
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
THL
/ t
/ t
/ t
propagation delay
PLH
An to Y
n
propagation delay
PLH
En to Y
n
output transition time 19
TLH
(°C)
T
amb
74HC
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
36
13
10
39
14
11
7
6
150
30
26
150
30
26
75
15
13
190
38
33
190
38
33
95
19
16
225
45
38
225
45
38
110
22
19
.
UNIT
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Figs 6 and 7
4.5
6.0
September 1993 5
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Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
A
n
E
n
1.0
1.0
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
T
amb
(°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25 −40 to +85 −40 to +125
UNIT
V
(V)
min. typ. max. min. max. min. max.
t
PHL
t
PHL
t
THL
/ t
/ t
/ t
propagation delay
PLH
An to Y
propagation delay
PLH
output transition time 7 15 19 22 ns 4.5 Figs 6 and 7
TLH
En to Y
n
n
16 35 44 53 ns 4.5 Fig.6
15 32 40 48 ns 4.5 Fig.7
WAVEFORMS
CC
September 1993 6
Page 7
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.6 Waveforms showing the address input (An) to
output (Yn) propagation delays and the output
transition times.
APPLICATION INFORMATION
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.7 Waveforms showing the enable input (En)
to output (Yn) propagation delays and the
output transition times.
Fig.8 1-of-16 decoder; LOW level output is selected.
September 1993 7
Fig.9 1-of-16 demultiplexer; logic level on selected
outputs follow the logic level on the data input.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
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