Datasheet 74 hct153 DATASHEETS (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT153

Dual 4-input multiplexer

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

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Philips Semiconductors Product speciﬁcation

Dual 4-input multiplexer 74HC/HCT153

FEATURES

• Non-inverting output

• Separate enable for each output

• Common select inputs

• See ‘253” for 3-state version

• Permits multiplexing from n lines to

1 line

• Enable line provided for cascading (n lines to 1 line)

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT153 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT153 have two identical 4-input multiplexers which select two bits of data from up to four sources selected by common data select inputs (S

, S1). The two 4-input

multiplexer circuits have individual active LOW output enable inputs (1E, 2E) which can be used to strobe the outputs independently. The outputs (1Y, 2Y) are forced LOW when the corresponding output enable inputs are HIGH.

The “153” is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels applied to S0 and S1.

The logic equations for the outputs are:

1Y = 1E.(1I0.S1.S0+1I1.S1.S0+

+1I2.S1.S0+1I3.S1.S0)

2Y = 2E.(2I0.S1.S0+2I1.S1.S0+

+2I2.S1.S0+2I3.S1.S0)

The “153” can be used to move data to a common output bus from a group of registers. The state of the select inputs would determine the particular register from which the data came. An alternative application is a function generator. The device can generate two functions or three variables. This is useful for implementing highly irregular random logic.

The “153” is similar to the “253” but has standard outputs.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

PHL

C C

I PD

/ t

PLH

propagation delay CL= 15 pF; VCC=5 V

, 2In to nY 14 16 ns

to nY 15 17 ns

E to nY 10 11 ns input capacitance 3.5 3.5 pF power dissipation capacitance per multiplexer notes 1 and 2 30 30 pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW): PD=CPD× V

× fi + ∑ (CL× V

× fo) where:

fi= input frequency in MHz fo= output frequency in MHz CL= output load capacitance in pF VCC= supply voltage in V ∑ (CL× V

2. For HC the condition is VI= GND to V

× fo) = sum of outputs

For HCT the condition is VI= GND to VCC− 1.5 V

TYPICAL

HC HCT

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic

Package Information”

UNIT

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Philips Semiconductors Product speciﬁcation

Dual 4-input multiplexer 74HC/HCT153

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 15 1 14, 2 S 6, 5, 4, 3 1I 7 1Y multiplexer output from source 1 8 GND ground (0 V) 9 2Y multiplexer output from source 2 10, 11, 12, 13 2I 16 V

E, 2E output enable inputs (active LOW)

, S

to 1I

to 2I

common data select inputs data inputs from source 1

data inputs from source 2 positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol.

Fig.3 IEC logic symbol. Fig.4 Functional diagram.

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Philips Semiconductors Product speciﬁcation

Dual 4-input multiplexer 74HC/HCT153

FUNCTION TABLE

SELECT

INPUTS

DATA INPUTS

OUTPUT ENABLE

OUTPUT

nEnY

XXXXXX H L L

L H H

L L L L

H H H H

L H X X

X X X X

X X L H

X X X X

L H X X

X X X X

X X L H

L L L L

Note

1. H = HIGH voltage level L = LOW voltage level X = don’t care

L H L H

Fig.5 Logic diagram.

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Philips Semiconductors Product speciﬁcation

Dual 4-input multiplexer 74HC/HCT153

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

propagation delay

PHL

/ t

PLH

1In to nY; 2In to nY

PHL

THL

/ t

propagation delay

PLH

Sn to nY

propagation delay

PLH

nE to nY

output transition time

TLH

(°C)

amb

74HC

+25 −40 to+85 −40 to+125

min. typ. max. min. max. min. max.

47 17 14

50 18 14

33 12 10

19 7 6

145 29 25

150 30 26

100 20 17

75 15 13

180 36 31

190 38 33

125 25 21

95 19 16

220 44 38

225 45 38

150 30 26

110 22 19

UNIT

TEST CONDITIONS

WAVEFORMS

(V)

2.0

4.5

Fig.6

6.0

2.0

4.5

Fig.7

6.0

2.0

4.5

Fig.7

6.0

2.0

4.5

Figs 6 and 7

6.0

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Philips Semiconductors Product speciﬁcation

Dual 4-input multiplexer 74HC/HCT153

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I

) for a unit load of 1 is given in the family specifications.

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

1In, 2I nE S

0.45

0.60

1.35

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

amb

(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

+25 −40 to+85 −40 to+125

UNIT

(V)

min. typ. max. min. max. min. max.

propagation delay

PHL

1In to nY;

19 34 43 51 ns 4.5 Fig.6

2In to nY

propagation delay

PLH

1In to nY;

13 24 30 36 ns 4.5 Fig.6

2In to nY

PHL

THL

/ t

propagation delay

PLH

Sn to nY

propagation delay

PLH

nE to nY

output transition time 7 15 19 22 ns 4.5

TLH

20 34 43 51 ns 4.5 Fig.7

14 27 34 41 ns 4.5 Fig.7

WAVEFORMS

Figs 6 and 7

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Philips Semiconductors Product speciﬁcation

Dual 4-input multiplexer 74HC/HCT153

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

Fig.6 Waveforms showing the input (1In, 2In) to output (1Y, 2Y) propagation delays and the output transition times.

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

Fig.7 Waveforms showing the select input (S0, S1) and the output enable input (E) to output (1Y, 2Y)

propagation delays and the output transition times.

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

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