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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT137
3-to-8 line decoder/demultiplexer
with address latches; inverting
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting
FEATURES
• Combines 3-to-8 decoder with 3-bit latch
• Multiple input enable for easy expansion or independent
controls
• Active LOW mutually exclusive outputs
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT137 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
74HC/HCT137
The 74HC/HCT137 are 3-to-8 line decoder/demultiplexers
with latches at the three address inputs (A
essentially combines the 3-to-8 decoder function with a
3-bit storage latch. When the latch is enabled (LE = LOW),
the “137” acts as a 3-to-8 active LOW decoder. When the
latch enable (LE) goes from LOW-to-HIGH, the last data
present at the inputs before this transition, is stored in the
latches. Further address changes are ignored as long as
LE remains HIGH.
The output enable input (E1 and E2) controls the state of
the outputs independent of the address inputs or latch
operation. All outputs are HIGH unless E1 is LOW and E
is HIGH.
The “137” is ideally suited for implementing
non-overlapping decoders in 3-state systems and strobed
(stored address) applications in bus oriented systems.
). The “137”
n
2
SYMBOL PARAMETER CONDITIONS
t
PHL/ tPLH
C
I
C
PD
propagation delay CL= 15 pF; VCC=5 V
A
to Y
n
n
LE to Y
E1 to Y
E
to Y
2
n
n
n
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 57 59 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
TYPICAL
UNIT
HC HCT
18 19 ns
17 21 ns
15 17 ns
15 15 ns
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
December 1990 2
.
Page 3
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3 A
4
5
6E
8 GND ground (0 V)
15, 14, 13, 12, 11, 10, 9, 7
16 V
to A
0
2
LE latch enable input (active LOW)
E
1
2
Y0 to Y
7
CC
data inputs
data enable input (active LOW)
data enable input (active HIGH)
multiplexer outputs
positive supply voltage
74HC/HCT137
Fig.1 Pin configuration. Fig.2 Logic symbol.
Fig.3 IEC logic symbol. Fig.4 Functional diagram.
December 1990 3
Page 4
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting
FUNCTION TABLE
INPUTS OUTPUTS
LE E
H L H X X X stable
X
X
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
E
1
X
L
H
H
H
H
H
H
H
H
A
2
X
X
L
H
L
H
L
H
L
H
A
0
X
X
L
L
H
H
L
L
H
H
A
1
2
X
X
L
L
L
L
H
H
H
H
Y
H
H
L
H
H
H
H
H
H
H
Y
0
1
H
H
H
L
H
H
H
H
H
H
Y
2
H
H
H
H
L
H
H
H
H
H
Y
3
H
H
H
H
H
L
H
H
H
H
74HC/HCT137
Y
H
H
H
H
H
H
L
H
H
H
Y
4
H
H
H
H
H
H
H
L
H
H
Y
5
H
H
H
H
H
H
H
H
L
H
Y
6
7
H
H
H
H
H
H
H
H
H
L
Fig.5 Logic diagram.
December 1990 4
Page 5
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
PHL
t
PHL
t
THL
t
W
t
su
t
h
/ t
/ t
/ t
/ t
/ t
propagation delay
PLH
PLH
PLH
PLH
TLH
An to Yn
propagation delay
LE to Y
propagation delay
E1 to Y
propagation delay
E2 to Y
output transition time
LE pulse width
HIGH
set-up time
An to LE
hold time
An to LE
n
n
n
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
58
21
17
55
20
16
50
18
14
50
18
14
19
7
6
50
11
10
4
9
3
50
3
10
1
9
1
30
3
6
1
5
1
180
36
31
190
38
32
145
29
25
145
29
25
75
15
13
74HC/HCT137
.
(°C) TEST CONDITIONS
T
amb
74HC
65
13
11
65
13
11
40
8
7
225
45
38
240
48
41
180
36
31
180
36
31
95
19
16
270
54
46
285
57
48
220
44
38
220
44
38
110
22
19
75
15
13
75
15
13
45
9
8
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
WAVEFORMS
V
CC
(V)
2.0
4.5
Fig.6
6.0
2.0
4.5
Fig.7
6.0
2.0
4.5
Fig.7
6.0
2.0
4.5
Fig.6
6.0
2.0
4.5
Fig.6
6.0
2.0
4.5
Fig.8
6.0
2.0
4.5
Fig.8
6.0
2.0
4.5
Fig.8
6.0
December 1990 5
Page 6
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
74HC/HCT137
address latches; inverting
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
A
n
E
1
E
2
1.50
1.50
1.50
LE 1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
) for a unit load of 1 is given in the family specifications.
CC
.
SYMBO L PARAMETER
t
PHL
t
PHL
t
PHL
t
PHL
t
THL
t
W
t
su
/ t
/ t
/ t
/ t
/ t
propagation delay
PLH
PLH
PLH
PLH
TLH
An to Y
propagation delay
LE to Y
propagation delay
E1 to Y
propagation delay
E2 to Y
output transition time
LE pulse width
HIGH
set-up time
n
n
n
n
An to LE
t
h
hold time
An to LE
T
amb
(°C)
TEST CONDITIONS
74HCT
+25 −40 to +85 −40 to +125
UNIT
WAVEFORMS
V
CC
(V)
min. typ. max. min. max. min. max.
22 38 48 57 ns 4.5 Fig.6
25 44 55 66 ns 4.5 Fig.7
20 37 46 56 ns 4.5 Fig.7
18 35 44 53 ns 4.5 Fig.6
7 15 19 22 ns 4.5 Fig.6
10 5 13 15 ns 4.5 Fig.8
10 2 13 15 ns 4.5 Fig.8
7 2 9 11 ns 4.5 Fig.8
December 1990 6
Page 7
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
Fig.6 Waveforms showing the address input (An) and
= 1.3 V; VI= GND to 3 V.
HCT: V
M
enable inputs (E2) to output (Yn) propagation
delays and the output transition times.
74HC/HCT137
(1) HC : VM= 50%; VI= GND to VCC.
Fig.7 Waveforms showing the enable input (E1, LE)
= 1.3 V; VI= GND to 3 V.
HCT: V
M
to output (Yn) propagation delays and the
output transition times.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
= 1.3 V; VI= GND to 3 V.
M
Fig.8 Waveforms showing the data set-up, hold times for An input to LE input and the latch enable pulse width.
APPLICATION INFORMATION
Fig.9 6-to-64 line decoder with input address storage.
December 1990 7
Page 8
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
74HC/HCT137
.
December 1990 8
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