Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT112
Dual JK flip-flop with set and reset;
negative-edge trigger
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Jun 10
Page 2
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
FEATURES
• Asynchronous set and reset
• Output capability: standard
• ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT112 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT112 are dual negative-edge triggered
JK-type flip-flops featuring individual nJ, nK, clock (n
CP),
set (nSD) and reset (nRD) inputs.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
/ t
PHL
PLH
f
max
C
I
C
PD
propagation delay CL= 15 pF; VCC=5 V
n
CP to nQ, nQ 1719ns
n
S
to nQ, nQ 1515ns
D
n
R
to nQ, nQ 1819ns
D
maximum clock frequency 66 70 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per flip-flop notes 1 and 2 27 30 pF
The set and reset inputs, when LOW, set or reset the
outputs as shown in the function table regardless of the
levels at the other inputs.
A HIGH level at the clock (n
nK inputs and data will be accepted. The nJ and nK inputs
control the state changes of the flip-flops as shown in the
function table. The nJ and nK inputs must be stable one
set-up time prior to the HIGH-to-LOW clock transition for
predictable operation.
Output state changes are initiated by the HIGH-to-LOW
transition of nCP.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
74HC/HCT112
CP) input enables the nJ and
TYPICAL
UNIT
HC HCT
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
1998 Jun 10 2
Page 3
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
ORDERING INFORMATION
TYPE
NUMBER
74HC112D;
74HCT112D
74HC112DB;
74HCT112DB
74HC112N;
74HCT112N
74HC112PW;
74HCT112PW
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 13 1
2, 12 1K, 2K data inputs; flip-flops 1 and 2
3, 11 1J, 2J data inputs; flip-flops 1 and 2
4, 10 1
5, 9 1Q, 2Q true flip-flop outputs
6, 7 1
8 GND ground (0 V)
15, 14 1
16 V
NAME DESCRIPTION VERSION
SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
CP, 2CP clock input (HIGH-to-LOW, edge triggered)
SD, 2S
D
Q, 2Q complement flip-flop outputs
RD, 2R
D
CC
set inputs (active LOW)
reset inputs (active LOW)
positive supply voltage
PACKAGE
74HC/HCT112
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
1998 Jun 10 3
Page 4
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
FUNCTION TABLE
OPERATING MODE
asynchronous set L H X X X H L
asynchronous reset H L X X X L H
undetermined L L X X X H L
toggle H H ↓ hh
load “0” (reset) H H ↓ lh L H
load “1” (set) H H ↓ hl H L
hold “no change” H H ↓ ll q
Note
1. If n
SD and nRD simultaneously go from LOW to HIGH, the output states will
be unpredictable.
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP
transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP
transition
q = lower case letters indicate the state of the referenced output one set-up
time prior to the HIGH-to-LOW CP transition
Fig.4 Functional diagram.
X = don’t care
↓ = HIGH-to-LOW CP transition
74HC/HCT112
INPUTS OUTPUTS
SDnRDnCP nJ nK nQ nQ
n
qq
q
Fig.5 Logic diagram (one flip-flop).
1998 Jun 10 4
Page 5
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
Output capability: standard
ICCcategory: flip-flops
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
74HC/HCT112
.
1998 Jun 10 5
Page 6
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
SYMBOL PARAMETER
t
/ t
PHL
PLH
t
/ t
PHL
PLH
t
/ t
PHL
PLH
t
/ t
PHL
PLH
t
/ t
THL
TLH
t
W
t
W
t
rem
t
rem
t
su
t
h
f
max
= 6 ns; CL= 50 pF
r=tf
propagation delay
nCP to nQ
propagation delay
nCP to nQ
propagation delay
nRD to nQ, nQ
propagation delay
nSD to nQ, nQ
output transition time
clock pulse width
HIGH or LOW
set or reset pulse width
LOW
removal time
nRD to nCP
removal time
nSD to nCP
set-up time
nJ, nK to nCP
hold time
nJ, nK to nCP
maximum clock pulse
frequency
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
55 175 220 265
16 30 37 45 6.0
55 175 220 265
16 30 37 45 6.0
58 180 225 270
17 31 38 46 6.0
50 155 295 235
14 26 33 40 6.0
19 75 95 110
6 13 16 19 6.0
80 22 100 120
14 6 17 20 6.0
80 22 100 120
14 6 17 20 6.0
80 22 125 150
14 6 21 26 6.0
80 −19 100 120
14 −6 17 20 6.0
80 19 100 120
14 6 17 20 6.0
0 −11 0 0
0 −3 0 0 6.0
6 20 4.8 4.0
35 71 28 24 6.0
74HC/HCT112
(°C) TEST CONDITIONS
T
amb
74HC
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
V
(V)
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
CC
WAVEFORMS
Fig.620 35 44 53 4.5
Fig.620 35 44 53 4.5
Fig.721 36 45 54 4.5
Fig.718 31 39 47 4.5
Fig.67 15 19 22 4.5
Fig.616 8 20 24 4.5
Fig.716 8 20 24 4.5
Fig.716 8 25 30 4.5
Fig.716 −7 20 24 4.5
Fig.616 7 20 24 4.5
Fig.60 −4 0 0 4.5
Fig.630 60 24 20 4.5
1998 Jun 10 6
Page 7
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
74HC/HCT112
negative-edge trigger
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: standard
ICCcategory: flip-flops
Note to HCT types
The value of additional quiescent supply current (∆I
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
SD, 2S
1
1K, 2K 0.6
1
1J, 2J 1
1
D
RD, 2R
D
CP, 2CP 1
0.5
0.65
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
) for a unit load of 1 is given in the family specifications.
CC
.
1998 Jun 10 7
Page 8
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
SYMBOL PARAMETER
t
/ t
PHL
PLH
/ t
t
PHL
PLH
t
/ t
PHL
PLH
t
/ t
PHL
PLH
/ t
t
THL
TLH
t
W
t
W
t
rem
t
rem
t
su
t
h
f
max
= 6 ns; CL= 50 pF
r=tf
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
propagation delay
nCP to nQ
propagation delay
nCP to nQ
propagation delay
nRD to nQ, nQ
propagation delay
nSD to nQ, nQ
21 35 44 53 ns 4.5 Fig.6
23 40 50 60 ns 4.5 Fig.6
22 37 46 56 ns 4.5 Fig.7
18 32 40 48 ns 4.5 Fig.7
output transition time 7 15 19 22 ns 4.5 Fig.6
clock pulse width
HIGH or LOW
set or reset pulse width
LOW
removal time
nRD to nCP
removal time
nSD to nCP
set-up time
nJ, nK to nCP
hold time
nJ, nK to nCP
maximum clock pulse
frequency
16 8 20 24 ns 4.5 Fig.6
18 10 23 27 ns 4.5 Fig.7
20 11 25 30 ns 4.5 Fig.7
20 −8 25 30 ns 4.5 Fig.7
16 7 20 24 ns 4.5 Fig.6
0 −7 0 0 ns 4.5 Fig.6
30 64 24 20 MHz 4.5 Fig.6
74HC/HCT112
T
(°C) TEST CONDITIONS
amb
74HCT
UNIT
V
(V)
CC
WAVEFORMS
1998 Jun 10 8
Page 9
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
74HC/HCT112
Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width,
the nJ, nK to nCP set-up times, the nCP to nJ, nK hold times, the output transition times and the maximum
clock pulse frequency.
handbook, full pagewidth
nCP INPUT
nSD INPUT
nRD INPUT
nQ OUTPUT
nQ OUTPUT
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
V
t
PHL
(1)
M
t
W
t
PLH
(1)
V
M
(1)
V
M
t
rem
t
V
t
PHL
PLH
t
W
(1)
M
t
rem
V
M
MBK218
(1)
Fig.7 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set
and reset pulse width and the nRD and nSD to nCP removal time.
1998 Jun 10 9
Page 10
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
D
c
y
Z
16
9
74HC/HCT112
SOT109-1
E
H
E
A
X
v M
A
pin 1 index
1
e
0 2.5 5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
mm
inches
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
A
max.
1.75
0.069
A1A2A
0.25
1.45
0.10
1.25
0.010
0.057
0.004
0.049
0.25
0.01
b
3
p
0.49
0.25
0.36
0.19
0.0100
0.019
0.0075
0.014
(1)E(1) (1)
cD
10.0
9.8
0.39
0.38
8
b
p
scale
eHELLpQZywv θ
4.0
1.27
3.8
0.16
0.050
0.15
w M
6.2
5.8
0.244
0.228
A
2
1.05
0.041
Q
A
1
detail X
1.0
0.7
0.4
0.6
0.028
0.039
0.020
0.016
(A )
L
p
L
0.25 0.1
0.25
0.01
0.01 0.004
A
3
θ
0.7
0.3
0.028
0.012
o
8
o
0
OUTLINE
VERSION
SOT109-1
IEC JEDEC EIAJ
076E07S MS-012AC
REFERENCES
1998 Jun 10 10
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
Page 11
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
D
c
y
Z
16
9
E
H
E
74HC/HCT112
SOT338-1
A
X
v M
A
pin 1 index
1
e
DIMENSIONS (mm are the original dimensions)
UNIT A1A2A3b
mm
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
A
max.
2.0
0.21
0.05
1.80
1.65
0.25
p
0.38
0.25
8
b
p
cD
0.20
6.4
0.09
6.0
w M
0 2.5 5 mm
scale
(1)E(1)
eHELLpQZywv θ
5.4
0.65 1.25
5.2
7.9
7.6
Q
A
2
A
1
detail X
1.03
0.9
0.63
0.7
(A )
L
p
L
3
θ
0.130.2 0.1
A
(1)
1.00
0.55
o
8
o
0
OUTLINE
VERSION
SOT338-1
IEC JEDEC EIAJ
REFERENCES
MO-150AC
1998 Jun 10 11
EUROPEAN
PROJECTION
ISSUE DATE
94-01-14
95-02-04
Page 12
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
D
seating plane
L
Z
16
e
b
b
1
9
A
w M
74HC/HCT112
SOT38-1
M
E
A
2
A
1
c
(e )
1
M
H
pin 1 index
1
0 5 10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT
mm
inches
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
A
max.
4.7 0.51 3.7
OUTLINE
VERSION
SOT38-1
min.
A
1 2
max.
0.15
IEC JEDEC EIAJ
050G09 MO-001AE
b
1.40
1.14
0.055
0.045
b
0.53
0.38
0.021
0.015
1
cEe M
0.32
0.23
0.013
0.009
REFERENCES
D
21.8
21.4
0.86
0.84
8
scale
(1) (1)
6.48
6.20
0.26
0.24
E
(1)
Z
e
0.30
1
0.15
0.13
M
L
3.9
3.4
E
8.25
7.80
0.32
0.31
EUROPEAN
PROJECTION
9.5
8.3
0.37
0.33
w
H
0.2542.54 7.62
0.010.100.0200.19
ISSUE DATE
92-10-02
95-01-19
max.
2.2
0.087
1998 Jun 10 12
Page 13
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
E
H
E
16
D
c
y
Z
9
74HC/HCT112
SOT403-1
A
X
v M
A
pin 1 index
18
w M
b
e
DIMENSIONS (mm are the original dimensions)
UNIT A1A2A3b
mm
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
A
max.
0.15
0.05
0.95
0.25
0.80
IEC JEDEC EIAJ
1.10
OUTLINE
VERSION
SOT403-1 MO-153
p
0.30
0.19
p
0 2.5 5 mm
scale
(1)E(2) (1)
cD
0.2
5.1
0.1
4.9
REFERENCES
eHELLpQZywv θ
4.5
0.65
4.3
A
6.6
6.2
Q
(A )
2
A
1
L
p
L
detail X
0.75
0.4
0.50
0.3
EUROPEAN
PROJECTION
3
A
θ
0.13 0.10.21.0
0.40
0.06
ISSUE DATE
94-07-12
95-04-04
o
8
o
0
1998 Jun 10 13
Page 14
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
DIP
S
OLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
R
EPAIRING SOLDERED JOINTS
stg max
). If the
74HC/HCT112
between 50 and 300 seconds depending on heating
method.
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
AVE SOLDERING
W
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
Even with these conditions:
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
SO, SSOP and TSSOP
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
1998 Jun 10 14
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
EPAIRING SOLDERED JOINTS
R
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
Page 15
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
74HC/HCT112
negative-edge trigger
one operation within 2 to 5 seconds between
270 and 320 °C.
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jun 10 15
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