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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT00
Quad 2-input NAND gate
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT00
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT00 provide the 2-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
= 25 °C; tr= tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
C
C
I
PD
/ t
PLH
propagation delay nA, nB to nY CL= 15 pF; VCC=5V 7 10 ns
input capacitance 3.5 3.5 pF
power dissipation capacitance per gate notes 1 and 2 22 22 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW):
PD
PD= CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC= supply voltage in V
Σ (CL× V
2. For HC the condition is VI= GND to V
2
× fo) = sum of outputs
CC
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
TYPICAL
UNIT
HC HCT
December 1990 2
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Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT00
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 4, 9, 12 1A to 4A data inputs
2, 5, 10, 13 1B to 4B data inputs
3, 6, 8, 11 1Y to 4Y data outputs
7 GND ground (0 V)
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUTS OUTPUT
nA nB nY
L
L
H
H
Note
1. H = HIGH voltage level
L = LOW voltage level
Fig.4 Functional diagram. Fig.5 Logic diagram (one gate).
L
H
L
H
H
H
H
L
December 1990 3
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Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT00
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICCcategory: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= tf= 6 ns; CL= 50 pF
r
SYMBOL PARAMETER
min. typ. max. min. max. min. max.
t
PHL
t
THL
/ t
/ t
propagation delay
PLH
TLH
nA, nB to nY
output transition
time
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
25
9
7
19
7
6
90
18
15
75
15
13
T
amb
74HC
(°C)
115
23
20
95
19
16
135
27
23
110
22
19
.
.
UNIT
ns
ns
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
2.0
4.5
Fig.6
6.0
2.0
4.5
Fig.6
6.0
Output capability: standard
ICCcategory: SSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆I
per input, multiply this value by the unit load coefficient shown in the table below.
CC
INPUT UNIT LOAD COEFFICIENT
nA, nB 1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= tf= 6 ns; CL= 50 pF
r
T
amb
(°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
V
(V)
CC
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
propagation delay
PLH
12 19 24 29 ns 4.5 Fig.6
nA, nB to nY
t
THL
/ t
output transition time 7 15 19 22 ns 4.5 Fig.6
TLH
December 1990 4
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Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT00
AC WAVEFORMS
HC : VM= 50%; VI= GND to V
HCT: VM= 1.3 V; VI= GND to 3 V.
CC
Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 5
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