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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC133
13-input NAND gate
Product specification
File under Integrated Circuits, IC06
September 1993
Page 2
Philips Semiconductors Product specification
13-input NAND gate 74HC133
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The HC133 is an high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The 74HC133 provides the 13-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PHL/tPLH
C
I
C
PD
= 25 °C; tr= tf= 6 ns
amb
propagation delay A..M to Y CL= 15 pF; VCC= 5 V 9 ns
input capacitance 3.5 pF
power dissipation per gate notes 1 and 2 19 pF
Notes to the quick reference data
1. C
is used to determine the dynamic power dissipation (PDin µW)
PD
PD= CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz; CL= output load capacitance in pF;
fo= output frequency in MHz; VCC= supply voltage in V;
∑ (CL× V
2. For HC the condition is VI= GND to V
2
× fo) = sum of the outputs.
CC
CC
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
PINS PIN POSITION MATERIAL CODE
74HC133N 16 DIL plastic SOT38
74HC133D 16 SO plastic SOT109A
See also
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
September 1993 2
Page 3
Philips Semiconductors Product specification
13-input NAND gate 74HC133
PINNING
PIN NO. SYMBOL NAME AND FUNCTION
1..7, 10.. 15 A.. G, H..M data input
8 GND ground (0 V)
9 Y data output
16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
September 1993 3
Page 4
Philips Semiconductors Product specification
13-input NAND gate 74HC133
Fig.4 Functional diagram;
Y=ABCDEFGHIJKLM.
FUNCTION TABLE
INPUTS OUTPUT
ABCDEFGH I JKLM Y
L
X
X
X
X
X
X
X
X
X
X
X
X
H
X
L
X
X
X
X
X
X
X
X
X
X
X
H
X
X
L
X
X
X
X
X
X
X
X
X
X
H
X
X
X
L
X
X
X
X
X
X
X
X
X
H
X
X
X
X
L
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
X
X
X
X
X
X
X
H
X
X
X
X
X
X
L
X
X
X
X
X
X
H
Fig.5 Logic diagram.
X
X
X
X
X
X
X
L
X
X
X
X
X
H
X
X
X
X
X
X
X
X
L
X
X
X
X
H
X
X
X
X
X
X
X
X
X
L
X
X
X
H
X
X
X
X
X
X
X
X
X
X
L
X
X
H
X
X
X
X
X
X
X
X
X
X
X
L
X
H
X
X
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
September 1993 4
Page 5
Philips Semiconductors Product specification
13-input NAND gate 74HC133
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICCcategory: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= tr= 6 ns; CL= 50 pF
f
SYMBOL PARAMETER
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
t
PHL/tPLH
propagation delay
A..M to Y
−
−
−
t
THL/tTLH
output transition
time
−
−
−
.
T
(°C) TEST CONDITIONS
amb
+25 −40 to +85 −40 to +125 UNIT
36
13
10
19
7
6
110
22
19
75
15
13
−
140
−
28
−
23
−
95
−
19
−
16
−
165
−
33
−
28
−
110
−
22
−
19
ns 2.0
ns 2.0
V
(V)
4.5
6.0
4.5
6.0
CC
WAVEFORMS
Fig.6
Fig.6
(1) HC: VM= 50%; VI= GND to VCC.
Fig.6 Waveforms showing the input (A, B, C, D, E, F, G, H, I, J, K, L, M) to output (Y) propagation delays and
the output transition times.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
September 1993 5
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