Page 1
Philips Semiconductors FAST Products Product specification
74F8965/74F89669-Bit address/data Futurebus transceiver, ADT
1
December 19, 1990 853 1526 01320
FEATURES
• 9–bit transceiver (both directions)
• Drives heavily loaded backplanes with
equivalent load impedances down to
10 ohms
• High drive (100mA) open collector
drivers on B port
• Reduced voltage swing (1V to 2V)
produces less noise and reduces
power consumption
• High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
• Compatible with IEEE 896 futurebus
standards and IEEE 1194 BTL standard
• Built–in precision band–gap reference
provides accurate receiver thresholds
and improved noise immunity
• Controlled output ramp and multiple
GND pins minimize ground bounce
• Glitch–free power up/power down
operation
• Guaranteed skew of less than 2ns
DESCRIPTION
The 74F8965 and 74F8966 are 9–bit
bidirectional latchable transceivers and are
intended to provide the electrical interface to
a high performance wired–OR bus. The B
port inverting drivers are low–capacitance
open collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a precision band
gap references for improved noise margins.
The B port interfaces to ’Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident wave switching is employed, therefore BTL propagation delays are short. Although the voltage swing is much less for
BTL, so is its receiver threshold region,
therefore noise margins are excellent.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8965 and 74F8966 A ports have TTL
3–state drivers and TTL receivers.
The B ports have standard BTL I/O with
100mA current sink capability. The B–to–A
path is a simple inverted buffered path. When
going from A–to–B the user may choose between a buffered path or a latching function.
The 74F8966 also has an idle arbitrator/multiple competitors output. The IAMC
output
compares, using a wired–OR configuration,
the data on the bus to the latched data presented to the bus. If the bus data matches the
data presented by the 74F8966 then IAMC
is
high. If the data doesn’t match then IAMC
goes low.
TYPE
TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT( TOTAL)
74F8965 3.5ns 80mA
74F8966 3.5ns 80mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
V
CC
= 5V ±10%, T
amb
= 0°C to +70°C
44–pin PLCC N74F8965A, N74F8966A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 – A8 TTL data inputs 1.0/0.033 20µA/20µA
B0 – B8 Data inputs with threshold circuitry 5.0/0.167 100µA/100µA
OEA, OEB0, OEB1
Output enable inputs 1.0/0.167 20µA/100µA
LS Latch select (active low) (’F8965) 1.0/0.167 20µA/100µA
IAREQ Idle arbitration request (active low) (’F8965) 1.0/0.167 20µA/100µA
LE Latch enable input (active low) 1.0/0.167 20µA/100µA
A0 – A8 3–state TTL outputs 150/40 3mA/24mA
B0 – B8 Open collector BTL outputs OC/166.7 OC/100mA
IAMC
Idle arbitration/multiple competitors output (’F8966)
OC/80 OC/48mA
Notes to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
Page 2
Philips Semiconductors FAST Products Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
2
PIN CONFIGURATION PLCC IEC/IEEE SYMBOL
74F8965
6 5 4 3 2 1
39
38
37
36
35
34
13
12
11
10
9
8
2422 23212019
44
33
18
7
A0
LOGIC
GND
A1 OEA OEB0 OEB
1
A8
2826 2725
43 42 41 40
B
0
32
31
30
29
17
16
15
14
LOGIC GND
A2
LOGIC GND
A3
LOGIC GND
A4
A5
LOGIC GND
A6
LOGIC GND
A7
LE
B8 B7
B1
BUS GND
B2
BUS GND
B3
BUS GND
B
4
BUS GND
B5
BUS GND
B
6
74F8965
41
2
C4
EN5
4D
39
37
35
33
31
29
27
25
MUX
1
3
LOGIC
V
CC
BUS
V
CC
BUS
GND
BUS
GND
LOGIC
GND
LOGIC
GND
LOGIC
V
CC
LS BUS
V
CC
BUS
GND
BUS
GND
6
8
10
12
13
15
17
19
23
1
44
22
2
1
1
1
4
&
EN3
G1/V2
PIN CONFIGURATION PLCC IEC/IEEE SYMBOL
74F8966
74F8966
6 5 4 3 2 1
39
38
37
36
35
34
13
12
11
10
9
8
2422 23212019
44
33
18
7
A0
LOGIC
GND
A1 OEA OEB0OEB
1
A8
2826 2725
43 42 41 40
B0
32
31
30
29
17
16
15
14
LOGIC GND
A2
LOGIC GND
A3
LOGIC GND
A4
A5
LOGIC GND
A6
LOGIC GND
A7
LE
B8 B7
B
1
BUS GND
B2
BUS GND
B3
BUS GND
B
4
BUS GND
B5
BUS GND
B
6
LOGIC
V
CC
BUS
V
CC
BUS
GND
BUS
GND
LOGIC
GND
IAMC
LOGIC
V
CC
IREQ BUS
V
CC
BUS
GND
BUS
GND
41
2
C4
EN5
4D
39
37
35
33
31
29
27
25
MUX
1
3
6
8
10
12
13
15
17
19
23
1
44
22
2
1
1
1
4
&
EN3
G1/V2/EN6
7 Z10
10
11
12
13
14
15
16
17
18
1
20
N7
Page 3
Philips Semiconductors FAST Products Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
3
LOGIC SYMBOL
A0 A1 A2 A3 A4 A5 A6 A7 A8
Logic VCC = Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18, 20
74F8965
1
44
23
22
2
OEB0
OEB1
LS
LE
OEA
4 6 8 10 12 13 15 17 19
B0 B1 B2 B3 B4 B5 B6 B7 B8
41 39 37 35 33 31 29 27 25
A0 A1 A2 A3 A4 A5 A6 A7 A8
74F8966
1
44
23
22
2
20
OEB0
OEB1
IAREQ
LE
OEA
IAMC
4 6 8 10 12 13 15 17 19
B0 B1 B2 B3 B4 B5 B6 B7 B8
41 39 37 35 33 31 29 27 25
Logic VCC = Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18
PIN DESCRIPTION
SYMBOL PINS TYPE NAME AND FUNCTION
A0 – A8 4, 6, 8, 10, 12, 13, 15, 17, 19 I/O Data inputs/TTL 3–state outputs
B0 – B8 41, 39, 37, 35, 33, 31, 29, 27, 25 I/O Data inputs / open collector outputs, high current drives.
OEB0 1 Input Output enable input. Enables the B outputs when high.
OEB1 44 Input Output enable input. Enables the B outputs when low.
OEA 2 Input Output enable input. Enables the A outputs when high.
LE 22 Input Latch enable input. Enables latch when low.
LS 23 Input Latch select input. Selects latch when low (74F8965).
IAREQ 23 Input Idle arbitration request input (74F8966).
IAMC 20 Output Idle arbitration/multiple competitors output (open collector output) (74F8966).
Bus GND 26, 28, 30, 32, 34, 36, 38, 40, 42 Ground Bus ground (0V)
Logic GND 5, 7, 9, 11, 14, 16, 18, 20 (74F8965) Ground Logic ground (0V)
Bus V
CC
24, 43 Power Positive supply voltages
Logic V
CC
3, 21 Power Positive supply voltages
Page 4
Philips Semiconductors FAST Products Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
4
LOGIC DIAGRAM FOR 74F8965
D
E
Q
41
39
37
35
33
31
29
27
25
A0
A1
A2
A3
A4
A5
A6
A7
A8
4
6
8
10
12
13
15
17
19
OEB0
OEB1
1
44
B0
B
1
B
2
B3
B
4
B
5
B
6
B
7
B
8
D
E
Q
D
E
Q
D
E
Q
D
E
Q
D
E
Q
D
E
Q
D
E
Q
D
E
Q
LS
LE
OEA
23
22
2
Logic VCC = Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18, 20
TTL levels
BTL levels
Page 5
Philips Semiconductors FAST Products Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
5
LOGIC DIAGRAM FOR 74F8966
D
E
Q
41
39
37
35
33
31
29
27
25
A0
A1
A2
A3
A4
A5
A6
A7
A8
4
6
8
10
12
13
15
17
19
OEB0
OEB1
1
44
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
IAREQ
LE
OEA
23
22
2
D
E
Q
D
E
Q
D
E
Q
D
E
Q
D
E
Q
D
E
Q
D
E
Q
D
E
Q
Logic VCC = Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18
TTL levels
BTL levels
IAMC
20
TTL level
48mA
open
collector
Page 6
Philips Semiconductors FAST Products Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
6
FUNCTION TABLE FOR 74F8965
INPUTS LATCH OUTPUTS OPERATING MODE
AIn Bn* OEB0 OEB1 LS OEA LE STATE An Bn
L – H L H L X X input H** An to Bn bypass latch
H – H L H L X X input L
L – H L L L L H input H** An to Bn transparent latch
H – H L L L L L input L
l – H L L L ↑ H input H** An to Bn latch and read
h – H L L L ↑ L input L
– – H L L H H H L H** An to Bn outputs latched and read
– – H L L H H L H L (preconditioned latch)
X – H L L L H NC input L An to Bn hold
X X L X X X X X X H** Disable Bn outputs
X X X H H X X X X H**
– L L H H H X X H input Bn to An
– H L H H H X X L input
– X X X X L X X Z X Disable An outputs
Notes to function table for 74F8965
1. H = High voltage level
2. h = High voltage level one setup time prior to the low–to–high LE
transition
3. L = Low voltage level
4. l = Low voltage level one setup time prior to the low–to–high LE
transition
5. NC= No change
6. X = Don’t care
7. Z = High impedance ”off’ state
8. – = Input not externally driven
9. ↑ = Low–to–high transition
10.H**= Goes to level of pullup voltage.
11.B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
FUNCTION TABLE FOR 74F8966
INPUTS LATCH OUTPUTS OPERATING MODE
AIn Bn* OEB0 OEB1 IAREQ LS OEA LE STATE An Bn IAMC
L – H L L H L X X input H** H** An to Bn bypass latch
H – H L L H L X X input L H**
L – H L L L L L H input H** H** An to Bn transparent latch
H – H L L L L L L input L H**
l – H L L L L ↑ H input H** H** An to Bn latch and read
h – H L L L L ↑ L input L H**
– – H L L L H H H L H** H** An to Bn outputs latched and read
– – H L L L H H L H L H** (preconditioned latch)
X – H L L L L H NC input NC H** An to Bn hold
X X L X X X X X X X H** H** Disable Bn outputs
X X X H H H X X X X H** H**
– L L H H H H X X H input H** Bn to An
– H L H H H H X X L input H**
– Bn L H H ↓* H H Bn Z Bn L Latch Bn data idle arbitration request
– Bn L H H ↓* H H Bn Z Bn H** (preconditioned latch)
– X X X X X L X X Z X X Disable An outputs
Page 7
Philips Semiconductors FAST Products Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
7
Notes to function table for 74F8966
1. H = High voltage level
2. h = High voltage level one setup time prior to the low–to–high LE
transition
3. L = Low voltage level
4. l = Low voltage level one setup time prior to the low–to–high LE
transition
5. NC= No change
6. X = Don’t care
7. Z = High impedance ”off’ state
8. – = Input not externally driven
9. ↑ = Low–to–high transition
10.↓* = High–to–low transition, latch must be preconditioned before IAREQ
11.H**= Goes to level of pullup voltage.
12.B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER RATING UNIT
–0.5 to +7.0 V
V
IN
Input voltage OEB0, OEB1, LEA, LE –0.5 to +7.0 V
A0 – A8, B0 – B8 –0.5 to +5.5 V
I
IN
–40 to +5 mA
–0.5 to V
CC
V
A0 – A8 48 mA
IAMC (74F8966 only) 96 mA
B0 – B8 200 mA
T
amb
0 to +70
°C
T
stg
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN NOM MAX UNIT
V
CC
4.5 5.0 5.5 V
V
IH
Except B0 – B8 2.0 V
B0 – B8 1.625 1.55 V
V
IL
Except B0 – B8 0.8 V
B0 – B8 1.475 V
I
Ik
–18 mA
I
OH
A0 – A8 –3 mA
V
OH
IAMC (74F8966 only) 4.5 V
A0 – A8 24 mA
I
OL
IAMC (74F8966 only) 48 mA
B0 – B8 100 mA
T
amb
0 +70
°C
V
CC
V
OUT
I
OUT
Supply voltage
Input current
Voltage applied to output in high output state
Current applied to output in low output
Operating free air temperature range
Storage temperature range
Supply voltage
High–level input voltage
Low–level input voltage
Input clamp current
High–level output current
High–level output voltage
Low–level output current
Operating free air temperature
Page 8
Philips Semiconductors FAST Products Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
8
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER TEST LIMITS UNIT
CONDITIONS
1
MIN TYP2MAX
I
OH
High–level output current B0 – B8 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA
IAMC (74F8966) VCC = MAX, VIL = MAX, VIH = MIN, VOH = 4.5V 100 µA
I
OFF
Power–off output current B0 – B8 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA
IAMC (74F8966) VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 4.5V 100 µA
V
OH
High-level output voltage A0 – A8
4
VCC = MAX, VIL = MAX, VIH = MIN, IOH = –3mA 2.4 V
CC
V
A0 – A8
4
VCC = MIN, I
OL
= 24mA 0.50 V
V
OL
Low-level output voltage IAMC (74F8966) VIL = MAX I
OL
= 48mA 0.50 V
B0 – B8 VIH = MIN I
OL
= 100mA 0.75 1.0 1.10 V
V
IK
Input clamp voltage VCC = MIN, II = I
IK
-1.2 V
I
I
Input current at
maximum input voltage
OEB0, OEB1,
OEA, LE
, LS,
IAREQ
VCC = MAX, VI = 7.0V 100 µA
A0 – A8, B0 –
B
8
VCC = MAX, VI = 5.5V 1 mA
I
IH
High–level input current
OEB0, OEB1,
OEA, LE
, LS,
IAREQ
VCC = MAX, VI = 2.7V 20 µA
B0 – B8 VCC = MAX, VI = 2.1V 100 µA
I
IL
Low–level input current
OEB0, OEB1,
OEA, LE
, LS,
IAREQ
VCC = MAX, VI = 0.5V –100 µA
B0 – B8 VCC = MAX, VI = 0.3V –100 µA
IIH + I
OZH
Off–state output current,
high–level voltage applied
VCC = MAX, V
O
= 2.7V 50
µA
IIL + I
OZL
Off–state output current,
low–level voltage applied
VCC = MAX, VI = 0.5V –50
µA
I
OS
VCC = MAX -60 -150 mA
I
CCH
VCC = MAX 80 140 mA
I
CC
Supply current (total) I
CCL
VCC = MAX, VIL = 0.5V 85 145 mA
I
CCZ
75 100 mA
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a
high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence
of parameter tests, I
OS
tests should be performed last.
4. Due to test equipment limitations, actual test conditions are for V
IH
=1.8V and VIL = 1.3V.
Short circuit output
3
current
A0 – A8
A0 – A8 only
Page 9
Philips Semiconductors FAST Products Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
9
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
T
amb
= +25°C T
amb
= 0°C to +70°C
SYMBOL PARAMETER TEST VCC = +5.0V
VCC = +5.0V ± 10%
UNIT
CONDITION
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
t
PLH
t
PHL
Propagation delay
B
n to An
Waveform 2
3.0
2.5
5.0
4.5
8.0
7.5
2.5
2.5
8.5
8.0
ns
t
PZH
t
PZL
Output enable time to high or low,
OEA to An
Waveform 5, 6
7.5
9.0
9.0
11.0
12.0
13.5
6.0
7.5
14.0
16.0
ns
t
PHZ
t
PLZ
Output disable from high or low,
OEA to An
Waveform 5, 6
3.0
4.0
5.0
6.0
8.0
9.0
2.5
4.0
9.0
10.0
ns
t
sk(o)
Skew between receivers in same package Waveform 4 0.5 1.0 1.0 ns
B PORT LIMITS
T
amb
= +25°C T
amb
= 0°C to +70°C
SYMBOL PARAMETER TEST VCC = +5.0V
VCC = +5.0V ± 10%
UNIT
CONDITION
CD = 30pF, RU = 9Ω CD = 30pF, RU = 9Ω
MIN TYP MAX MIN MAX
t
PLH
t
PHL
Propagation delay
An to B
n (transparent latch)
Waveform 2
2.5
3.0
4.0
5.0
7.0
7.5
2.0
2.5
8.0
9.0
ns
t
PLH
t
PHL
Propagation delay
An to Bn (bypass latch)
Waveform 2
1.0
1.5
3.0
3.0
5.5
5.5
1.0
1.0
6.0
6.5
ns
t
PLH
t
PHL
Propagation delay
LE
to Bn
Waveform 1, 2
3.0
4.0
5.0
5.5
8.0
8.5
3.0
3.5
8.5
9.5
ns
t
PLH
t
PHL
Output enable/disable time,
OEB0 to B
n
Waveform 2
4.0
5.0
6.0
6.5
8.5
9.5
3.5
3.5
10.0
11.5
ns
t
PLH
t
PHL
Output enable/disable time,
OEB
1 to Bn
Waveform 1
5.5
3.0
7.5
5.0
10.0
8.0
5.0
2.5
11.0
8.5
ns
t
PLH
t
PHL
Propagation delay
IAREQ or LS to Bn
Waveform 1, 2
4.5
2.0
7.5
6.5
10.0
9.5
4.0
2.0
11.0
11.0
ns
t
TLH
t
THL
Transition time, Bn port
10% to 90%, 90% to 10%
Test circuit and
waveforms
2.0
2.0
1.0
1.0
3.0
3.0
ns
t
sk(o)
Skew between drivers in same package Waveform 4 1.0 2.0 2.0 ns
IAMC PORT LIMITS (74F8966 only)
T
amb
= +25°C T
amb
= 0°C to +70°C
SYMBOL PARAMETER TEST VCC = +5.0V
VCC = +5.0V ± 10%
UNIT
CONDITION
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
t
PLH
t
PHL
Propagation delay
An to IAMC
(latches preset)
Waveform 2
10.5
7.0
14.5
12.0
18.0
15.0
9.5
6.0
20.0
17.5
ns
t
PLH
t
PHL
Propagation delay
IAREQ
to IAMC
Waveform 2
6.5
2.5
8.0
4.5
11.0
7.0
6.0
2.0
11.5
8.0
ns
Page 10
Philips Semiconductors FAST Products Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
10
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25°C T
amb
= 0°C to +70°C
SYMBOL PARAMETER TEST VCC = +5.0V
VCC = +5.0V ± 10%
UNIT
CONDITION
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
tsu(H)
t
su
(L)
Setup time, high or low
An
to LE
Waveform 3
2.5
0.0
3.0
0.0
ns
t
h
(H)
t
h
(L)
Hold time, high or low
An
to LE
Waveform 3
4.0
2.5
5.0
3.0
ns
tw(L) LE pulse width, low Waveform 3 4.0 4.5 ns
AC WAVEFORMS
V
M
V
M
V
M
V
M
Waveform 1. Propagation delay for data or
output enable to output
Waveform 3. Data setup and hold times and LE
pulse width
Waveform 5. 3–state output enable time to high level
and output disable time from high level
Waveform 6. 3-state output enable time to low level
and output disable time from low level
V
M
V
M
VMV
M
V
M
V
M
tsu(L)
t
su
(H)
th(L) th(H)
V
M
V
M
V
M
t
PHZ
t
PZH
VOH -0.3V
0V
V
M
V
M
V
M
t
PLZ
t
PZL
VOL +0.3V
An
OEA
An
B
n, IAMC
Bn, LS, LE,
OEB1, IAREQ
t
PLH
t
PHL
V
M
tw(L)
V
M
V
M
V
M
V
M
Waveform 2. Propagation delay for data or
output enable to output
An, Bn. IAMC
t
PHL
t
PLH
An, Bn, LS, LE,
OEB0, IAREQ
An, Bn
LE
OEA
Waveform 4. Output skew
V
M
V
M
t
sk(o)
An, Bn
An, Bn
Notes to AC waveforms
1. For all waveforms, V
M
= 1.5V.
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
Page 11
Philips Semiconductors FAST Products Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
11
TEST CIRCUITS AND WAVEFORMS
t
w
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
NEGATIVE
PULSE
POSITIVE
PULSE
t
w
AMP (V)
Low V
Low V
t
THL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLHtTHL
Input pulse definition
V
CC
family
74F
D.U.T.
PULSE
GENERATOR
R
L
C
L
R
T
V
IN
V
OUT
Test circuit for 3–state outputs on A port
DEFINITIONS:
R
L
= Load resistor; see AC electrical characteristics for value.
C
L
= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
R
U
= Pull up resistor; see AC electrical characteristics for value.
CD= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
t
THL (tf
)
t
TLH (tr
)
t
TLH (tr
)
AMP (V)
amplitude
V
M
R
L
7.0V
V
CC
D.U.T.
PULSE
GENERATOR
C
D
R
T
V
IN
V
OUT
Test circuit for outputs on B port
R
U
7.0V
Low V
SWITCH POSITION
TEST SWITCH
closed
openAll other
t
PLZ
, t
PZL
A port 3.0V 0.0V 1.5V 1MHz 500ns 2.5ns 2.5ns
B port 3.0V 1.0V 1.5V 1MHz 500ns 4.0ns 4.0ns
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