Page 1
Philips Semiconductors FAST Products Product specification
74F8962/8963
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
1
March 11, 1993 853–1425 09230
FEATURES
•Octal latched transceiver
•Drives heavily loaded backplanes with
equivalent load impedances down to 10Ω
•High drive (100mA) open collector drivers
on B port
•Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
•High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
•Compatible with IEEE 896 futurebus
standards
•Built–in precision band–gap reference
provides accurate receiver thresholds and
improved noise immunity
•Multiple GND pins minimize ground bounce
•Glitch–free power up/power down
operation
DESCRIPTION
The 74F8962 and 74F8963 are octal
bidirectional latched transceivers and are
intended to provide the electrical interface to
a high performance wired-OR bus. The B port
inverting drivers are low-capacitance open
collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a 150mV
threshold region.
The B port interfaces to ‘Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident wave switching to 9Ω is guaranteed.
The voltage swing is much less for BTL, so is
its receiver threshold region, therefore noise
margins are excellent.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8962 and 74F8963 A ports have TTL
3-state drivers and TTL receivers with a latch
function.
The 74F8963 is the non-inverting version of
74F8962.
TYPE
TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT( TOTAL)
74F8962 6.5ns 90mA
74F8963 5.5ns 90mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
V
CC
= 5V ±10%, T
amb
= 0°C to +70°C
44–pin Quad Flat Pack
1
N74F8962Y, N74F8963Y
44–pin Plastic Leaded Chip Carrier N74F8962A, N74F8963A
Note to ordering information
1. Flatpack package is not available at this time.
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
AI0 – AI8 PNP latched inputs 1.0/0.167 20µA/100µA
B0 – B8 Data inputs with threshold circuitry 5.0/0.167 100µA/100µA
OEAB, OEBA Output enable inputs (active low) 1.0/0.033 20µA/20µA
LEAB, LEBA Latch enable inputs (active low) 1.0/0.033 20µA/20µA
AO0 – AO8 3–state outputs 150/40 3mA/24mA
B0 – B8 Open collector outputs OC/166.7 OC/100mA
Notes to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
Page 2
Philips Semiconductors FAST Products Product specification
74F8962/8963
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
March 11, 1993
2
PIN CONFIGURATION FLATPACK AND PLCC IEC/IEEE SYMBOL
74F8962
6 5 4 3 2 1
39
38
37
36
35
34
13
12
11
10
9
8
2422 23212019
44
33
18
7
AO0AI1AO1GND AI0
V
CC
OEBA
AO7AI7GND
2826 2725
43 42 41
40
LEBA BO GND B1
32
31
30
29
17
16
15
14
AI2
AO2
A13
AO3
AI4
GND
AO4
AI5
AO5
AI6
AO6
AI8 AO8
V
CC
LEAB OEAB
B8
GND B7
GND
B2
GND
B3
GND
B4
GND
B5
GND
B6
GND
74F8962
42
EN1
EN2
EN3
EN4
1
24
25
43
44
40
38
36
34
32
30
28
26
2
3
4
5
7
8
9
10
11
13
14
15
16
17
19
20
21
22
2
4
3D
PIN DESCRIPTION
SYMBOL PINS TYPE NAME AND FUNCTION
AI0 – AI8 2, 4, 7, 9, 11, 14, 16, 19, 21 Input PNP latched inputs.
B0 – B8 42, 40, 38, 36, 34, 32, 30, 28, 26 I/O Data input / open collector output, high current drives.
OEAB 25 Input Output enable input. Enables the B outputs when low.
OEBA 44 Input Output enable input. Enables the A outputs when high.
LEAB 24 Input Latch enable input. Enables the AB latches low.
LEBA 43 Input Latch enable input. Enables the BA latches low.
AO0 – AO8 3, 5, 8, 10, 13, 15, 17, 20, 22 Output TTL 3–state outputs.
GND 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41 Ground Grounds
V
CC
1, 23 Power Positive supply voltages
Page 3
Philips Semiconductors FAST Products Product specification
74F8962/8963
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
March 11, 1993
3
LOGIC SYMBOL FOR 74F8962
OEBA
OEAB
LEAB
LEBA
AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8
42 40 38
B0 B1 B2
36 34 32 30 28 26
B6 B7 B8B3 B4 B5
V
CC
= Pin 1, 23
GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41
74F8962
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 21 22
25
24
43
44
LOGIC SYMBOL FOR 74F8963
OEBA
OEAB
LEAB
LEBA
AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8
42 40 38
B0 B1 B2
36 34 32 30 28 26
B6 B7 B8B3 B4 B5
74F8963
25
24
43
44
V
CC
= Pin 1, 23
GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 21 22
Page 4
Philips Semiconductors FAST Products Product specification
74F8962/8963
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
March 11, 1993
4
LOGIC DIAGRAM
B0
B1
B2
B3
B4
B5
B6
B7
B8
DataEQ
V
CC
= Pin 1, 23
GND = Pin 6, 12, 18, 27, 29, 31, 33, 37, 39, 41
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
42
40
38
36
34
32
30
28
26
AI0
AO0
AI1
AO1
AI2
AO2
AI3
AO3
AI4
AO4
AI5
AO5
AI6
AO6
AI7
AO7
AI8
AO8
2
3
4
5
7
8
9
10
11
13
14
15
16
17
19
20
21
22
OEAB
LEBA
LEAB
OEBA
25
43
24
44
B0
B1
B2
B3
B4
B5
B6
B7
B8
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
DataEQ
Data
E
Q
42
40
38
36
34
32
30
28
26
AI0
AO0
AI1
AO1
AI2
AO2
AI3
AO3
AI4
AO4
AI5
AO5
AI6
AO6
AI7
AO7
AI8
AO8
2
3
4
5
7
8
9
10
11
13
14
15
16
17
19
20
21
22
OEAB
LEBA
LEAB
OEBA
25
43
24
44
74F8962
74F8963
Data
E
Page 5
Philips Semiconductors FAST Products Product specification
74F8962/8963
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
March 11, 1993
5
FUNCTION TABLE FOR 74F8962
INPUTS LATCH STATES OUTPUTS OPERATING MODE
AIn Bn* LEAB LEBA OEAB OEBA AB BA AOn Bn
H H L L H H H H Z X
L L L L H H L L Z X B and AO disabled
X X H H H H Qn Qn Z X
H – L X L H H Qn Z L AO 3–state, transparent data from AI to B
L – L X L H L Qn Z H**
X H X L H L Qn H L X B disabled, transparent data from B to AO
X L X L H L Qn L H X
X X H X L H Qn Qn Z Qn AO 3–state, latched data to B
X X X H H L Qn Qn Qn X B disabled, latched to AO
X X H H L L Qn Qn Qn Qn Latched state to AO and B
H – L L L L H L H L Read back from AI to B to AO
L – L L L L L H L H** (both latches transparent)
Notes to function table for 74F8962
1. H = High voltage level
2. L = Low voltage level
3. X = Don’t care
4. – = Input not externally driven
5. Z = High impedance ”off’ state
6. Q
n
= High or low voltage level one setup time prior to the low–to–high LEXX transition.
7. H**= Goes to level of pullup voltage.
8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
FUNCTION TABLE FOR 74F8963
INPUTS LATCH STATES OUTPUTS OPERATING MODE
AIn Bn* LEAB LEBA OEAB OEBA AB BA AOn Bn
H H L L H H L L Z X
L L L L H H H H Z X B and AO disabled
X X H H H H Qn Qn Z X
H – L X L H L Qn Z H AO 3–state, transparent data from AI to B
L – L X L H H Qn Z L
X H X L H L Qn L H X B disabled, transparent data from B to AO
X L X L H L Qn H L X
X X H X L H Qn Qn Z Qn AO 3–state, latched data to B
X X X H H L Qn Qn Qn X B disabled, latched to AO
X X H H L L Qn Qn Qn Qn Latched state to AO and B
H – L L L L L L H H** Read back from AI to B to AO
L – L L L L H L L L (both latches transparent)
Notes to function table for 74F8963
1. H = High voltage level
2. L = Low voltage level
3. X = Don’t care
4. – = Input not externally driven
5. Z = High impedance ”off” state
6. Q
n
= High or low voltage level one setup time prior to the low–to–high LEXX transition.
7. H**= Goes to level of pullup voltage.
8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
Page 6
Philips Semiconductors FAST Products Product specification
74F8962/8963
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
March 11, 1993
6
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER RATING UNIT
V
CC
–0.5 to +7.0 V
V
IN
Input voltage OEBA, OEAB, LEBA, LEAB –0.5 to +7.0 V
AI0 – AI8, B0 – B8 –0.5 to +5.5 V
I
IN
–40 to +5 mA
V
OUT
–0.5 to V
CC
V
I
OUT
Current applied to output in low output state AO0 – AO8 48 mA
B0 – B8 200 mA
T
amb
0 to +70
°C
T
stg
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN NOM MAX UNIT
V
CC
4.5 5.0 5.5 V
V
IH
Except B0 – B8 2.0 V
B0 – B8 1.62 V
V
IL
Except B0 – B8 0.8 V
B0 – B8 1.47 V
I
Ik
–18 mA
I
OH
AO0 – AO8 –3 mA
I
OL
AO0 – AO8 24 mA
B0 – B8 100 mA
T
amb
0 +70
°C
Supply voltage
Input current
Voltage applied to output in high output state
Operating free air temperature range
Storage temperature range
Supply voltage
High–level input voltage
Low–level input voltage
Input clamp current
High–level output current
Low–level output current
Operating free air temperature
Page 7
Philips Semiconductors FAST Products Product specification
74F8962/8963
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
March 11, 1993
7
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER TEST LIMITS UNIT
CONDITIONS
1
MIN TYP2MAX
I
OH
High-level output current B0 – B8 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA
I
OFF
Power-off output current B0 – B8 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA
V
OH
High-level output voltage AO0 – AO84VCC = MAX, VIL = MAX, VIH = MIN, IOH = –3mA 2.5 V
CC
V
AO0 – AO84VCC = MIN, I
OL
= 24mA 0.50 V
V
OL
Low-level output voltage B0 – B8 VIL = MAX I
OL
= 100mA 0.75 1.0 1.10 V
VIH = MIN I
OL
= 4mA 0.40 V
V
IK
Input clamp voltage VCC = MIN, II = I
IK
-1.2 V
I
I
Input current at
maximum input voltage
OEAB, OEBA,
LEAB, LEBA,
AI0 – AI8
VCC = MAX, VI = 7.0V 100 µA
B0 – B8 VCC = MAX, VI = 5.5V 1 mA
I
IH
High-level input current
OEAB, OEBA,
LEAB, LEBA,
AI0 – AI8
VCC = MAX, VI = 2.7V 20 µA
B0 – B8 VCC = MAX, VI = 2.1V 100 µA
I
IL
Low-level input current
OEAB, OEBA,
LEAB
, LEBA,
AI0 – AI8
VCC = MAX, VI = 0.5V –100 µA
B0 – B8 VCC = MAX, VI = 0.3V –100 µA
I
OZH
Off state output current,
high-level voltage applied
VCC = MAX, V
O
= 2.7V 50
µA
I
OZL
Off state output current,
low-level voltage applied
VCC = MAX, VI = 0.5V –50
µA
I
OS
Short circuit output
AO0 –
AO8
’F8960
74F8962
VCC = MAX, Bn = 1.3V, OEBA = 0.8V,
OEAB
= 2.7V
-60 -150 mA
current
3
74F8963
VCC = MAX, Bn = 1.8V, OEBA = 0.8V,
OEAB
= 2.7V
I
CCH
VCC = MAX 80 110 mA
I
CC
Supply current (total) I
CCL
VCC = MAX, VIL = 0.5V 105 145 mA
I
CCZ
80 110 mA
NOTES TO DC ELECTRICAL CHARACTERISTICS
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. Due to test equipment limitations, actual test conditions are for V
IH
= 1.8V and VIL = 1.3V.
AO0 – AO8
only
Page 8
Philips Semiconductors FAST Products Product specification
74F8962/8963
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
March 11, 1993
8
AC ELECTRICAL CHARACTERISTICS FOR 74F8962
A PORT LIMITS
T
amb
= +25°C T
amb
= 0°C to
+70
°C
T
amb
= 0°C to
+70
°C
SYMBOL PARAMETER TEST VCC = +5.0V
VCC = +5.0V ± 10% VCC = +5.0V ± 5%
UNIT
CONDITION CL = 50pF,
R
L
= 500Ω
CL = 50pF,
R
L
= 500Ω
CL = 50pF,
R
L
= 500Ω
MIN TYP MAX MIN MAX MIN MAX
t
PLH
t
PHL
Propagation delay
Bn
to AOn
Waveform 1, 2
5.0
3.5
7.0
5.5
10.0
8.5
4.5
3.5
11.0
8.5
4.5
3.5
10.5
8.5
ns
t
PLH
t
PHL
Propagation delay
LEBA to AOn
Waveform 1, 2
5.5
4.5
7.0
6.5
10.0
9.5
5.0
4.5
10.0
9.5
5.0
4.5
10.0
9.5
ns
t
PZH
t
PZL
Output enable time to high or
low, OEBA
to AOn
Waveform 5, 6
7.5
8.5
9.5
10.5
12.5
13.0
6.5
7.5
13.5
14.5
6.5
7.5
13.0
13.5
ns
t
PHZ
t
PLZ
Output disable from high or low,
OEBA
to AOn
Waveform 5, 6
3.5
4.5
5.5
6.5
8.5
9.5
2.5
4.0
10.0
10.0
2.5
4.0
9.0
9.5
ns
t
sk(o)
Skew between receivers in
same package
Waveform 4 1.5 2.0 4.0 4.0 ns
B PORT LIMITS
T
amb
= +25°C T
amb
= 0°C to
+70
°C
T
amb
= 0°C to
+70
°C
SYMBOL PARAMETER TEST VCC = +5.0V
VCC = +5.0V ± 10% VCC = +5.0V ± 5%
UNIT
CONDITION CD = 30pF,
R
U
= 9Ω
CD = 30pF,
R
U
= 9Ω
CD = 30pF,
R
U
= 9Ω
MIN TYP MAX MIN MAX MIN MAX
t
PLH
t
PHL
Propagation delay
AIn
to Bn
Waveform 1, 2
3.5
4.0
5.5
6.0
8.5
9.5
3.0
3.5
9.0
10.5
3.0
3.5
9.0
10.0
ns
t
PLH
t
PHL
Propagation delay
LEAB
to Bn
Waveform 1, 2
4.0
5.0
6.0
7.0
8.5
10.5
3.5
5.0
9.5
10.5
3.5
5.0
9.5
10.5
ns
t
PLH
t
PHL
Output enable/disable time
OEBA
to Bn
Waveform 1
3.5
3.0
5.0
4.0
8.0
8.0
3.0
2.5
8.5
8.5
3.0
2.5
8.0
8.5
ns
t
TLH
t
THL
Transition time, Bn port
10% to 90%, 90% to 10%
Test circuit and
waveforms
1.0
1.0
1.2
2.0
1.6
2.5
1.0
1.0
2.5
3.5
1.0
1.0
2.5
3.5
ns
t
sk(o)
Skew between drivers in same
package
Waveform 4 0.5 2.5 3.0 3.0 ns
AC SETUP REQUIREMENTS FOR 74F8962
LIMITS
T
amb
= +25°C T
amb
= 0°C to
+70
°C
T
amb
= 0°C to
+70
°C
SYMBOL PARAMETER TEST VCC = +5.0V
VCC = +5.0V ± 10% VCC = +5.0V ± 5%
UNIT
CONDITION CL = 50pF,
R
L
= 500Ω
CL = 50pF,
R
L
= 500Ω
CL = 50pF,
R
L
= 500Ω
MIN TYP MAX MIN MAX MIN MAX
tsu(H)
t
su
(L)
Setup time, high or low
AIn
to LEAB
Waveform 3
3.0
1.0
3.5
2.0
3.0
1.5
ns
t
h
(H)
t
h
(L)
Hold time, high or low
AIn
to LEAB
Waveform 3
3.0
0.0
3.5
0.0
3.0
0.0
ns
tsu(H)
t
su
(L)
Setup time, high or low
Bn
to LEBA
Waveform 3
2.0
1.0
2.5
1.0
2.0
1.0
ns
th(H)
t
h
(L)
Hold time, high or low
Bn
to LEBA
Waveform 3
3.0
1.5
3.5
2.0
3.0
2.0
ns
tw(L) LEAB or LEBA pulse width, low Waveform 3 4.5 4.5 4.5 ns
Page 9
Philips Semiconductors FAST Products Product specification
74F8962/8963
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
March 11, 1993
9
AC ELECTRICAL CHARACTERISTICS FOR 74F8963
A PORT LIMITS
T
amb
= +25°C T
amb
= 0°C to
+70
°C
T
amb
= 0°C to
+70
°C
SYMBOL PARAMETER TEST VCC = +5.0V
VCC = +5.0V ± 10% VCC = +5.0V ± 5%
UNIT
CONDITION CL = 50pF,
R
L
= 500Ω
CL = 50pF,
R
L
= 500Ω
CL = 50pF,
R
L
= 500Ω
MIN TYP MAX MIN MAX MIN MAX
t
PLH
t
PHL
Propagation delay
Bn
to AOn
Waveform 1, 2
3.5
2.5
5.5
4.0
8.0
7.0
3.0
2.0
9.0
7.5
3.0
2.0
8.0
7.5
ns
t
PLH
t
PHL
Propagation delay
LEBA to AOn
Waveform 1, 2
6.0
4.0
7.5
5.5
10.0
8.5
5.0
3.5
11.5
9.0
5.0
3.5
10.0
8.5
ns
t
PZH
t
PZL
Output enable time to high or
low, OEBA
to AOn
Waveform 5, 6
9.0
10.0
11.0
12.0
15.0
16.0
8.5
9.0
16.5
18.0
8.5
9.0
15.5
16.5
ns
t
PHZ
t
PLZ
Output disable time from high or
low, OEBA
to AOn
Waveform 5, 6
4.0
5.5
6.0
7.0
9.0
11.0
3.0
5.0
10.5
12.0
3.0
5.0
9.5
11.0
ns
t
sk(o)
Skew between receivers in
same package
Waveform 4 1.5 2.0 4.0 4.0 ns
B PORT LIMITS
T
amb
= +25°C T
amb
= 0°C to
+70
°C
T
amb
= 0°C to
+70
°C
SYMBOL PARAMETER TEST VCC = +5.0V
VCC = +5.0V ± 10% VCC = +5.0V ± 5%
UNIT
CONDITION CD = 30pF,
R
U
= 9Ω
CD = 30pF,
R
U
= 9Ω
CD = 30pF,
R
U
= 9Ω
MIN TYP MAX MIN MAX MIN MAX
t
PLH
t
PHL
Propagation delay
AIn
to Bn
Waveform 1, 2
2.0
2.0
4.0
3.5
6.5
6.5
1.5
1.5
7.0
6.5
2.0
2.0
7.0
6.5
ns
t
PLH
t
PHL
Propagation delay
LEAB
to Bn
Waveform 1, 2
3.5
2.5
5.0
4.0
8.0
7.0
3.0
2.0
8.5
8.0
3.5
2.5
8.5
8.0
ns
t
PLH
t
PHL
Output enable/disable time
OEBA
to Bn
Waveform 1
3.5
3.0
5.5
5.0
9.0
7.5
2.5
2.5
9.5
8.5
2.5
2.5
9.0
8.0
ns
t
TLH
t
THL
Transition time, Bn port
10% to 90%, 90% to 10%
Test circuit and
waveforms
1.0
1.0
1.2
2.0
1.6
2.5
1.0
1.0
2.5
3.5
1.0
1.0
2.5
3.5
ns
t
sk(o)
Skew between drivers in same
package
Waveform 4 0.5 2.0 3.0 3.0 ns
AC SETUP REQUIREMENTS FOR 74F8963
LIMITS
T
amb
= +25°C T
amb
= 0°C to
+70
°C
T
amb
= 0°C to
+70
°C
SYMBOL PARAMETER TEST VCC = +5.0V
VCC = +5.0V ± 10% VCC = +5.0V ± 5%
UNIT
CONDITION CL = 50pF,
R
L
= 500Ω
CL = 50pF,
R
L
= 500Ω
CL = 50pF,
R
L
= 500Ω
MIN TYP MAX MIN MAX MIN MAX
tsu(H)
t
su
(L)
Setup time, high or low
AIn
to LEAB
Waveform 3
4.0
1.0
4.5
1.5
4.0
1.0
ns
t
h
(H)
t
h
(L)
Hold time, high or low
AIn
to LEAB
Waveform 3
2.5
0.0
3.0
0.0
2.5
0.0
ns
tsu(H)
t
su
(L)
Setup time, high or low
Bn
to LEBA
Waveform 3
2.0
1.0
2.5
1.0
2.0
1.0
ns
th(H)
t
h
(L)
Hold time, high or low
Bn
to LEBA
Waveform 3
2.5
1.0
3.0
1.5
3.0
1.0
ns
tw(L) LEAB or LEBA pulse width, low Waveform 3 4.5 5.5 5.5 ns
Page 10
Philips Semiconductors FAST Products Product specification
74F8962/8963
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
March 11, 1993
10
AC WAVEFORMS
V
M
V
M
V
M
V
M
Waveform 1. Propagation delay for data or output enable or
latch enable to output
Waveform 3. Data setup and hold times and LEAB
/LEBA pulse widths
Waveform 5. 3–state output enable time to high level
and output disable time from high level
Waveform 6. 3-state output enable time to low level
and output disable time from low level
V
M
V
M
VMV
M
V
M
V
M
tsu(L)
t
su
(H)
th(L) th(H)
V
M
V
M
V
M
t
PHZ
t
PZH
VOH -0.3V
0V
V
M
V
M
V
M
t
PLZ
t
PZL
VOL +0.3V
An
OEAB
An
AOn, Bn
AIn, Bn,
LEAB
, LEBA
OEAB
t
PLH
t
PHL
V
M
tw(L)
V
M
V
M
V
M
V
M
Waveform 2. Propagation delay for data or latch enable to
output
An, Bn
t
PHL
t
PLH
AIn, Bn,
LEAB
, LEBA
AIn, Bn
LEAB
, LEBA
OEAB
Waveform 4. Output skew
V
M
V
M
t
sk(o)
AOn, Bn
AOn, Bn
NOTES TO AC WAVEFORMS
1. For all waveforms, V
M
= 1.5V.
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
t
w
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
NEGATIVE
PULSE
POSITIVE
PULSE
t
w
AMP (V)
Low V
Low V
t
THL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLHtTHL
Input pulse definition
V
CC
family
74F
D.U.T.
PULSE
GENERATOR
R
L
C
L
R
T
V
IN
V
OUT
Test circuit for 3–state outputs on A port
DEFINITIONS:
R
L
= Load resistor; see AC electrical characteristics for value.
CL= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
RU= Pull up resistor; see AC electrical characteristics for value.
C
D
= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
t
THL (tf
)
t
TLH (tr
)
t
TLH (tr
)
AMP (V)
amplitude
V
M
R
L
7.0V
V
CC
D.U.T.
PULSE
GENERATOR
C
D
R
T
V
IN
V
OUT
Test circuit for outputs on B port
R
U
7.0V
Low V
SWITCH POSITION
TEST SWITCH
closed
openAll other
t
PLZ
, t
PZL
A port 3.0V 0.0V 1.5V 1MHz 500ns 2.5ns 2.5ns
B port 3.0V 1.0V 1.5V 1MHz 500ns 4.0ns 4.0ns
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