Page 1
INTEGRATED CIRCUITS
74F841/842/843/845/846
Bus interface latches
Product specification
Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08
IC15 Data Handbook
1999 Jun 23
Page 2
Philips Semiconductors Product specification
Bus interface latches
74F841/74F842/74F843/
74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State)
74F843 9-bit bus interface latch, non-inverting (3-State)
74F845/74F846 8-bit bus interface latches, non-inverting/inverting (3-State)
FEA TURES
•High speed parallel latches
•Extra data width for wide address/data paths or buses carrying
parity
•High impedance NPN base input structure minimizes bus loading
•IIL is 20µA vs 1000A for AM29841 series
•Buffered control inputs to reduce AC effects
•Ideal where high speed, light loading, or increased fan-in are
required as with MOS microprocessors
•Positive and negative over-shoots are clamped to ground
•3-State outputs glitch free during power-up and power-down
•48mA sink current
•Slim dual in-line 300 mil package
•Broadside pinout
•Pin-for-pin and function compatible with AMD AM29841-846
series
TYPICAL
TYPE
74F841, 74F842 5.5ns 60mA
74F843, 74F845 5.5ns 75mA
74F846 6.2ns 60mA
PROPAGATION
DELA Y
TYPICAL
SUPPLY CURRENT
(TOTAL)
DESCRIPTION
The 74F841–74F846 bus interface latch series are designed to
provide extra data width for wider address/data paths of buses
carrying parity.
The 74F841–74F846 series are funcitonally an pin compatible to the
AMD AM29841–AM29846 series.
The 74F841 consists of ten D-type latches with 3-State outputs. The
flip-flops appear transparent to the data when Latch Enable (LE) is
High. This allows asynchronous operation, as the output transition
follows the data in transition. On the LE High-to-Low transition, the
data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (OE
When OE
The 74F842 is the inverted output version of the 74F841.
The 74F843 consists of nine D-type latches with 3-State outputs. In
addition to the LE and OE
(MR
interfacing in high performance systems. When MR
outputs are Low if OE
entered into the latch. When PRE
is Low, PRE overrides MR.
The 74F845 consists of eight D-type latches with 3-State outputs. In
addition to the LE, OE
addtitional OE
OE
The multiple Ouptut Enables (OE
control of the interface, e.g., CS
The 74F846 is the inverted output version of the 74F845.
is High the output is in the High-impedance state.
pins, the 74F843 has a Master Reset
) pin and Preset (PRE) pin. These pins are ideal for parity bus
is Low. When MR is High, data can be
, MR and PRE pins, the 74F845 has two
pins making a total of three Output Enables (OE0,
1, OE2) pins.
74F845/74F846
) is Low.
is Low, the
is Low, the outputs are High, if OE
0, OE1, OE2) allow multi-user
, DMA, and RD/WR.
ORDERING INFORMATION
PACKAGES
24-pin plastic Slim DIP (300 mil) N74F841N, N74F842N, N74F843N, N74F845N, N74F846N SOT222-1
24-pin plastic SOL N74F841D, N74F842D, N74F843D, N74F845D, N74F846D SOT137-1
COMMERCIAL RANGE
VCC = 5V±10%; T
= 0°C to +70°C
amb
PACKAGE DRAWING
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
Dn Data inputs 1.0/0.033 20µA/20µA
LE Latch Enable input 1.0/0.033 20µA/20µA
OE, OEn Output Enable input (active Low) 1.0/0.033 20µA/20µA
MR Master Reset input (active Low) 1.0/0.033 20µA/20µA
PRE Preset input (active Low) 1.0/0.033 20µA/20µA
Qn Data outputs 1200/80 24mA/48mA
Qn Data outputs 1200/80 24mA/48mA
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F(U.L.)
HIGH/LOW
NUMBER
LOAD VALUE
HIGH/LOW
1999 Jun 23 853–1208 21851
2
Page 3
Philips Semiconductors Product specification
Bus interface latches
PIN CONFIGURATION for 74F841
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
D8
11
D9
GND
12 13
LOGIC SYMBOL for 74F841
24
23
22
21
20
19
18
17
16
15
14
SF01279
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
LE
74F841/74F842/74F843/
74F845/74F846
PIN CONFIGURATION for 74F842
1
CC
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
D8
11
D9
12 13
GND
LOGIC SYMBOL for 74F842
24
23
22
21
20
19
18
17
16
15
14
SF01282
V
CC
Q0
Q
1
Q
2
Q
3
4
Q
Q
5
Q6
7
Q
Q
8
Q
9
LE
3456 78910
2
D0LED1 D2 D3 D4 D5 D6 D7 D8
13
1
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
= Pin 24
V
CC
GND = Pin 12
23 22 21 20 19 18 17 16 15 14
LOGIC SYMBOL (IEEE/IEC) for 74F841
1
EN
13
C1
1 D
4
5
6
7
8
9
10
SF01280
232
223
21
20
19
18
17
16
15
1411
11
D9
13
1
= Pin 24
V
CC
GND = Pin 12
3456 78910
2
D0LED1 D2 D3 D4 D5 D6 D7 D8
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
11
D9
SF01283
LOGIC SYMBOL (IEEE/IEC) for 74F842
1
EN
13
C1
1 D
4
5
6
7
8
9
10
11
232
223
21
20
19
18
17
16
15
14
1999 Jun 23
SF01281
SF01284
3
Page 4
Philips Semiconductors Product specification
Bus interface latches
PIN CONFIGURATION for 74F843
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
D8
11
MR
12 13
GND
LOGIC SYMBOL for 74F843
24
23
22
21
20
19
18
17
16
15
14
SF01285
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
PRE
LE
74F841/74F842/74F843/
74F845/74F846
3456 78910
2
13
14 PRE
11 MR
1OE
= Pin 24
V
CC
GND = Pin 12
D0LED1 D2 D3 D4 D5 D6 D7 D8
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
23 22 21 20 19 18 17 16 15
LOGIC SYMBOL (IEEE/IEC) for 74F843
1
EN
11
R
14
S2
13
C1
1 D
4
5
6
7
8
9
10
SF01286
232
223
21
20
19
18
17
16
15
1999 Jun 23
SF01287
4
Page 5
Philips Semiconductors Product specification
Bus interface latches
PIN CONFIGURATION for 74F845
1
OE
0
2
1
OE
3
D0
4
D1
5
D2
6
D3
7
D4
8
D5
9
D6
10
D7
11
MR
12 13
GND
LOGIC SYMBOL for 74F845
3456 78910
24
23
22
21
20
19
18
17
16
15
14
SF01291
V
CC
OE2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PRE
LE
74F841/74F842/74F843/
74F845/74F846
PIN CONFIGURATION for 74F846
1
OE
0
2
1
OE
3
D0
4
D1
5
D2
6
D3
7
D4
8
D5
9
D6
10
D7
11
MR
12 13
GND
LOGIC SYMBOL for 74F846
3456 78910
24
23
22
21
20
19
18
17
16
15
14
SF01294
V
OE2
Q
Q
Q
Q
Q
Q
Q
Q
PRE
LE
CC
0
1
2
3
4
5
6
7
13
14 PRE
11 MR
1 OE0
2 OE1
23 OE2
V
= Pin 24
CC
GND = Pin 12
D0LED1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
22 21 20 19 18 17 16 15
SF01292
LOGIC SYMBOL (IEEE/IEC) for 74F845
1
&
2
23
14
11
13
4
5
6
7
8
9
10
EN
S2
R
C1
1 D
13
14 PRE
11 MR
1 OE0
2 OE1
23 OE2
V
= Pin 24
CC
GND = Pin 12
D0LED1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
22 21 20 19 18 17 16 15
SF01295
LOGIC SYMBOL (IEEE/IEC) for 74F846
1
&
2
23
14
11
13
223
21
20
19
18
17
16
15
4
5
6
7
8
9
10
S2
R
C1
1 D
EN
223
21
20
19
18
17
16
15
1999 Jun 23
SF01293A
SF01296A
5
Page 6
Philips Semiconductors Product specification
INPUTS
Transparent
Latched
Bus interface latches
LOGIC DIAGRAM for 74F841
D0
2
D
LQ
13
LE
1
OE
VCC = Pin 24
GND = Pin 12
LOGIC DIAGRAM for 74F842
D0
2
D1
3
D
LQ
23
Q0
D1
3
D2
4
22
Q1
D2
4
D
LQ
Q2
D3
5
D
LQ
21
D3
5
D4
6
20
Q3
D4
6
D
LQ
Q4
D5
7
D
LQ
19
D5
7
D6
8
18
Q5
D6
8
74F841/74F842/74F843/
74F845/74F846
D
LQ
C
Q6
D7
9
D
LQ
17
D7
9
D8
10
16
Q7
D8
10
D9
11
D
LQ
15
Q8
D9
11
D
LQ
14
Q9
SF01297
13
LE
1
OE
VCC = Pin 24
GND = Pin 12
D
LQ
23
Q0
D
LQ
Q1
D
LQ
22
21
Q2
D
LQ
Q3
D
LQ
20
D
LQ
19
Q4
FUNCTION TABLE for 74F841 and 74F842
OUTPUTS
74F841 74F842
OE LE Dn Qn Qn
L H L L H
L H H H L
L ↓ l L H
L ↓ h H L
H X X Z Z High Impedance
L L X NC NC Hold
H = High voltage level
L = Low voltage level
h = High state one setup time before the High-to-Low LE transition
l = Low state one setup time before the High-to-Low LE transition
↓ = High-to-Low transition
X = Don’t care
NC= No change
Z = High impedance “off” state
18
Q5
p
D
LQ
C
Q6
D
LQ
17
D
LQ
16
Q7
OPERATING MODE
15
Q8
D
LQ
14
Q9
SF01298
1999 Jun 23
6
Page 7
Philips Semiconductors Product specification
INPUTS
Transparent
Latched
Bus interface latches
74F841/74F842/74F843/
LOGIC DIAGRAM for 74F843
PRE
MR
OE
VCC = Pin 24
GND = Pin 12
D0
14
11
13
LE
1
2
DP
LQ
C
Q0
D1
23
3
DP
LQ
C
Q1
D2
4
DP
LQ
C
22
Q2
21
D3
5
DP
LQ
C
Q3
D4
20
6
DP
LQ
C
Q4
D5
7
DP
LQ
C
19
Q5
D6
18
8
DP
LQ
FUNCTION TABLE for 74F843
OUTPUTS
74F843
OE PRE MR LE Dn Qn
L L X X X H Preset
L H L X X L Clear
L H H H L L
L H H H H H
L H H ↓ l L
L H H ↓ h H
H X X X X Z High Impedance
L H H L X NC Hold
H = High voltage level
L = Low voltage level
h = High state one setup time before the High-to-Low LE transition
l = Low state one setup time before the High-to-Low LE transition
↓ = High-to-Low transition
X = Don’t care
NC= No change
Z = High impedance “off” state
74F845/74F846
D7
9
DP
C
LQ
C
Q6
17
Q7
16
OPERATING MODE
p
D8
10
DP
LQ
C
SF01299
Q8
15
1999 Jun 23
7
Page 8
Philips Semiconductors Product specification
INPUTS
Transparent
Latched
Bus interface latches
LOGIC DIAGRAM for 74F845
D0
14
PRE
DP
LQ
11
MR
13
LE
1
OE
0
2
OE
1
23
V
= Pin 24
CC
GND = Pin 12
LOGIC DIAGRAM for 74F846
OE2
PRE
D0
14
74F841/74F842/74F843/
74F845/74F846
3
3
D1
4
DP
C
LQ
22
Q0
D1
4
D2
5
DP
C
LQ
21
Q1
D2
5
D3
6
DP
C
LQ
20
Q2
D3
6
D4
7
DP
C
LQ
19
Q3
D4
7
D5
8
DP
18
Q4
D5
LQ
C
8
C
D6
17
Q5
D6
9
DP
LQ
C
Q6
9
D7
10
DP
LQ
C
16
D7
10
15
Q7
SF01301
V
= Pin 24
CC
GND = Pin 12
MR
OE
OE
OE2
DP
LQ
C
11
13
LE
1
0
2
1
23
22
Q0
DP
LQ
C
Q1
DP
LQ
21
DP
20
Q2
LQ
C
C
19
Q3
DP
LQ
C
Q4
DP
LQ
C
18
Q5
FUNCTION TABLE for 74F845 and 74F846
OUTPUTS
74F845 74F846
OE PRE MR LE Dn Qn Qn
L L X X X H H Preset
L H L X X L L Clear
L H H H L L H
L H H H H H L
L H H ↓ l L H
L H H ↓ h H L
H X X X X Z Z High Impedance
L H H L X NC NC Hold
H = High voltage level
L = Low voltage level
h = High state one setup time before the High-to-Low LE transition
l = Low state one setup time before the High-to-Low LE transition
↓ = High-to-Low transition
X = Don’t care
NC= No change
Z = High impedance “off” state
DP
LQ
C
17
16
Q6
OPERATING MODE
p
DP
LQ
C
Q7
SF01302
15
1999 Jun 23
8
Page 9
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
Bus interface latches
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.
SYMBOL
V
V
I
IN
V
I
OUT
T
T
CC
IN
OUT
amb
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to V
Current applied to output in Low output state 84 mA
Operating free-air temperature range 0 to +70 °C
Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
V
V
V
I
I
I
T
CC
IH
IL
IK
OH
OL
amb
Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
Input clamp current –18 mA
High-level output current –24 mA
Low-level output current 48 mA
Operating free-air temperature range 0 +70 °C
PARAMETER RATING UNIT
74F841/74F842/74F843/
74F845/74F846
CC
LIMITS
MIN NOM MAX
V
1999 Jun 23
9
Page 10
Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
I
15mA
VOHHigh-level output voltage
CC
,
I
24mA
VOLLow-level output voltage
CC
,
I
y
74F845
Bus interface latches
74F841/74F842/74F843/
74F845/74F846
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
LIMITS
MIN TYP2MAX
±10%V
±5%V
±10%V
±5%V
IK
V
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
CC
= –
p
p
IK
Input clamp voltage VCC = MIN, II = I
VCC = MIN,
VIL = MAX, VIH = MIN
VCC = MIN,
VIL = MAX, VIH = MIN
OH
= –
OH
IOL = 32mA ±10%V
IOL = 48mA ±5%V
Input current at maximum input voltage VCC = 0.0V, VI = 7.0V 100 µA
High-level input current VCC = MAX, VI = 2.7V 20 µA
Low-level input current VCC = MAX, VI = 0.5V –20 µA
Off-state output current,
High-level voltage applied
Off-state output current,
Low-level voltage applied
Short-circuit output current
74F841
74F842
Supply current
(total)
74F843
74F845
74F846
3
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
VCC = MAX, VO = 2.7V 50 µA
VCC = MAX, VO = 0.5V –50 µA
VCC = MAX –100 –225 mA
VCC = MAX
VCC = MAX
VCC = MAX
VCC = MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
= 5V, T
CC
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
amb
= 25°C.
, the use of high-speed test apparatus and/or sample-and-hold
OS
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter test, I
tests should be performed last.
OS
2.2 V
CC
2.2 3.3 V
CC
2.0 V
CC
2.0 V
CC
CC
CC
0.38 0.55 V
0.38 0.55 V
–0.73 –1.2 V
50 65 mA
60 80 mA
70 92 mA
40 60 mA
65 90 mA
60 90 mA
65 90 mA
75 100 mA
85 115 mA
50 70 mA
70 95 mA
70 95 mA
1999 Jun 23
10
Page 11
Philips Semiconductors Product specification
74F841
74F842
Bus interface latches
74F841/74F842/74F843/
74F845/74F846
AC ELECTRICAL CHARACTERISTICS for 74F841/74F842
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT
CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
Dn to Qn
Propagation delay
LE to Qn
Propagation delay
Dn to Qn
Propagation delay
LE to Qn
Output enable time
High or Low-level OEn to Qn or Qn
Output disable time
High or Low-level OEn to Qn or Qn
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Waveform 5
Waveform 6
Waveform 5
Waveform 6
2.0
2.5
4.5
4.0
3.5
3.0
5.0
4.5
2.5
4.0
1.0
1.0
4.0
4.5
6.5
6.0
5.5
5.0
7.0
6.5
4.5
6.0
4.5
5.0
7.5
7.5
9.5
9.0
8.5
8.0
10.0
9.0
8.0
9.5
8.0
8.0
= 0°C to +70°C
amb
2.0
2.5
4.0
3.5
4.5
4.0
3.0
3.0
2.0
3.0
1.0
1.0
8.0
8.0
10.0
9.5
9.0
8.5
10.5
9.5
8.5
10.5
8.5
8.5
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS for 74F841/74F842
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT
CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MIN MAX
ts(H)
ts(L)
th(H)
th(L)
Setup time, High or Low
Dn to LE
Hold time, High or Low
Dn to LE
74F841
Waveform 4
Waveform 4
0.0
0.0
2.5
3.0
tw(H) LE pulse width, High Waveform 4 3.5 4.0 ns
th(H)
th(L)
Hold time, High or Low
Dn to LE
74F842
Waveform 4
3.0
3.5
tw(H) LE pulse width, High Waveform 4 3.0 3.0 ns
= 0°C to +70°C
amb
1.0
1.0
3.0
4.0
3.5
4.5
ns
ns
ns
1999 Jun 23
11
Page 12
Philips Semiconductors Product specification
Bus interface latches
74F841/74F842/74F843/
74F845/74F846
AC ELECTRICAL CHARACTERISTICS for 74F843/74F845
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT
CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
Dn to Qn
Propagation delay
LE to Qn
Propagation delay
PRE to Qn
Propagation delay
MR to Qn
Output enable time
High or Low-level OEn to Qn
Output disable time
High or Low-level OEn to Qn
Waveform 1, 2
Waveform 1, 2
2.0
2.5
4.5
4.0
4.5
4.5
6.5
6.0
7.5
8.0
9.5
8.5
Waveform 3 3.5 5.5 8.5 3.0 9.0 ns
Waveform 3 2.0 4.5 7.5 2.0 8.0 ns
Waveform 5
Waveform 6
Waveform 5
Waveform 6
2.5
4.0
1.0
1.0
4.5
6.0
4.5
5.0
7.5
9.5
8.0
8.0
= 0°C to +70°C
amb
2.0
2.5
4.5
4.0
2.0
3.0
1.0
1.0
8.5
8.5
10.0
8.5
8.0
10.5
8.5
8.5
ns
ns
ns
ns
AC SETUP REQUIREMENTS for 74F843/74F845
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT
CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MIN MAX
ts(H)
ts(L)
th(H)
th(L)
Setup time, High or Low
Dn to LE
Hold time, High or Low
Dn to LE
Waveform 4
Waveform 4
1.0
1.0
3.0
4.0
tw(H) LE pulse width, High Waveform 4 3.0 3.0 ns
tw(L) PRE pulse width, Low Waveform 3 4.0 5.0 ns
tw(H) MR pulse width, Low Waveform 3 4.0 5.0 ns
t
REC
t
REC
PRE recovery time Waveform 3 0.0 0.0 ns
MR recovery time Waveform 3 3.5 4.5 ns
= 0°C to +70°C
amb
0.0
0.0
3.0
4.0
ns
ns
1999 Jun 23
12
Page 13
Philips Semiconductors Product specification
Bus interface latches
74F841/74F842/74F843/
74F845/74F846
AC ELECTRICAL CHARACTERISTICS for 74F846
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT
CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
Dn to Qn
Propagation delay
LE to Qn
Propagation delay
PRE to Qn
Propagation delay
MR to Qn
Output enable time
High or Low-level OEn to Qn
Output disable time
High or Low-level OEn to Qn
Waveform 1, 2
Waveform 1, 2
3.5
3.0
5.0
4.5
5.5
5.0
7.0
6.5
8.5
8.0
10.0
9.0
Waveform 3 3.5 5.5 8.5 3.0 9.5 ns
Waveform 3 5.0 7.0 10.0 4.5 10.5 ns
Waveform 5
Waveform 6
Waveform 5
Waveform 6
2.5
4.0
1.0
1.0
5.0
6.0
4.5
5.0
7.5
9.5
8.0
8.0
= 0°C to +70°C
amb
3.0
3.0
5.0
4.5
2.0
3.0
1.0
1.0
9.5
8.5
10.5
9.5
8.0
10.5
8.5
8.5
ns
ns
ns
ns
AC SETUP REQUIREMENTS for 74F846
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT
CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MIN MAX
ts(H)
ts(L)
th(H)
th(L)
Setup time, High or Low
Dn to LE
Hold time, High or Low
Dn to LE
Waveform 4
Waveform 4
0.0
0.0
3.0
4.0
tw(H) LE pulse width, High Waveform 4 3.0 3.0 ns
tw(L) PRE pulse width, Low Waveform 3 4.0 5.0 ns
tw(H) MR pulse width, Low Waveform 3 4.0 5.0 ns
t
REC
t
REC
PRE recovery time Waveform 3 0.0 0.0 ns
MR recovery time Waveform 3 3.5 4.5 ns
= 0°C to +70°C
amb
0.0
0.0
3.0
4.0
ns
ns
1999 Jun 23
13
Page 14
Philips Semiconductors Product specification
Bus interface latches
74F841/74F842/74F843/
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Dn, LE
Qn
V
M
t
PLH
V
Waveform 1. Propagation Delay, Non-Inverting Path
PRE,
MR
LE
Qn, Qn
tw(L)
V
M
t
PLH
t
PHL
V
M
t
REC
V
M
V
M
V
M
t
PHL
M
V
M
SF01303
Dn, LE
Q
n
Waveform 2. Propagation Delay, Inverting Path
Dn
LE
V
V
M
M
th(H)ts(H)
V
M
Waveform 4. Data Setup and Hold Times
74F845/74F846
V
M
t
PHL
V
V
M
M
tw(H)
V
M
t
PLH
V
M
SF01304
V
V
M
M
th(L)ts(L)
V
M
SF01306
n
Qn, Q
V
M
SF01305
Waveform 3. Master Reset and Preset Pulse Width,
Master Reset and Preset to Output Delay,
and Master Reset and Preset to Latch Enable Recovery Time
OEn
Qn, Qn
V
t
PZH
M
V
M
t
PHZ
V
M
VOH -0.3V
0V
SF00509
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
OEn
Qn, Q
n
V
t
PZL
M
V
V
M
t
PLZ
M
VOL +0.3V
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable time from Low Level
3.5V
SF00510
1999 Jun 23
14
Page 15
Philips Semiconductors Product specification
Bus interface latches
TEST CIRCUIT AND WAVEFORMS
V
CC
V
PULSE
GENERATOR
IN
R
T
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
t
PLZ
PZL
closed
closed
All other open
DEFINITIONS:
R
= Load resistor;
L
see AC electrical characteristics for value.
= Load capacitance includes jig and probe capacitance;
C
L
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
D.U.T.
V
OUT
74F841/74F842/74F843/
74F845/74F846
t
7.0V
R
L
R
C
L
L
NEGATIVE
PULSE
POSITIVE
PULSE
90%
10%
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
w
V
M
10%
)
)
t
w
t
TLH (tr
t
THL (tf
)
)
90%
V
M
Input Pulse Definition
INPUT PULSE REQUIREMENTS
V
amplitude
3.0V
M
1.5V
rep. rate
1MHz 500ns
t
w
t
TLH
2.5ns 2.5ns
OUT
of
family
74F
90%
10%
t
THL
SF00777
AMP (V)
0V
AMP (V)
0V
1999 Jun 23
15
Page 16
Philips Semiconductors Product specification
Bus interface latches
74F841/74F842/74F843/
74F845/74F846
DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1
1999 Jun 23
16
Page 17
Philips Semiconductors Product specification
Bus interface latches
74F841/74F842/74F843/
74F845/74F846
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
1999 Jun 23
17
Page 18
Philips Semiconductors Product specification
Bus interface latches
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
74F841/74F842/74F843/
74F845/74F846
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Date of release: 06-99
Document order number: 9397 750 06143
1999 Jun 23
18
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