Page 1
INTEGRATED CIRCUITS
74F821/822/823/824/825/826
Bus interface registers
Product specification 1996 Jan 05
IC15 Data Handbook
Page 2
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
74F821 10-bit bus interface register, non-inverting (3-State)
74F822 10-bit bus interface register, inverting (3-State)
74F823 9-bit bus interface register, non-inverting (3-State)
74F824 9-bit bus interface register, inverting (3-State)
74F825 8-bit bus interface register, non-inverting (3-State)
74F826 8-bit bus interface register, inverting (3-State)
FEATURES
•High speed parallel registers with positive edge-triggered D-type
flip-flops
•High performance bus interface buffering for wide data/address
paths or busses carrying parity
•High impedance PNP base inputs for reduced loading (20µA in
high and low states)
•I
is 20µA vs 1000µA for AM29821 series
IL
•Buffered control inputs to reduce AC effects
•Ideal where high speed, light loading, or increased fan-in as
required with MOS microprocessor
•Positive and negative over-shoots are clamped to ground
•3-State outputs glitch free during power-up and power-down
•Slim Dip 300 mil package
•Broadside pinout compatible with AMD AM 29821-29826 series
•Outputs sink 64mA and source 24mA
•Industrial temperature range available (–40°C to +85°C) for
74F823
DESCRIPTION
The 74F821 series bus interface registers are designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of busses
carrying parity.
The 74F821/74F822 are buffered 10-bit wide versions of the popular
74F374/74F534 functions.
The 74F822 is the inverted output version of 74F821.
The 74F823 and 74F824 are 9-bit wide buffered registers with clock
enable (CE
interfacing in high microprogrammed systems.
The 74F824 is the inverted version of 74F823.
The 74F825 and 74F826 are 8-bit buffered registers with all the
74F823/74F824 controls plus output enable (OE
allow multiuser control of the interface, e.g., CS
They are ideal for uses as an output port requiring high I
The 74F826 is the inverted version of 74F825.
74F821, 74F822 180MHz 75mA
74F823, 74F824 180MHz 70mA
74F825, 74F826 180MHz 65mA
) and master reset (MR) which are ideal for parity bus
0, OE1, OE2) to
, DMA, and RD/WR.
TYPE
TYPICAL
f
max
TYPICAL
SUPPLY CURRENT
(TOTAL)
OL/IOH
.
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
24-pin plastic slim DIP (300mil)
24-pin plastic SOL
1996 Jan 05 853-1304 16195
COMMERCIAL RANGE
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
N74F821N, N74F822N, N74F823N,
N74F824N, N74F825N, N74F826N
N74F821D, N74F822D, N74F823D,
N74F824D, N74F825D, N74F826D
2
INDUSTRIAL RANGE
V
= 5V ±10%,
CC
T
= –40°C to +85°C
amb
I74F823N SOT222-1
I74F823D SOT137-1
PKG. DWG. #
Page 3
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
Dn Data inputs 1.0/1.0 20µA/0.6mA
74F821 CP Clock input 1.0/1.0 20µA/0.6mA
74F822 OE Output enable input (active low) 1.0/3.0 20µA/1.8mA
Qn, Qn Data outputs 1200/106.7 24mA/64mA
Dn Data inputs 1.0/1.0 20µA/0.6mA
CP Clock input 1.0/1.0 20µA/0.6mA
74F823 CE Clock enable input (active low) 1.0/3.0 20µA/1.8mA
74F824 MR Master reset input (active low) 1.0/3.0 20µA/1.8mA
OE Output enable input (active low) 1.0/3.0 20µA/1.8mA
Qn, Qn Data outputs 1200/106.7 24mA/64mA
Dn Data inputs 1.0/1.0 20µA/0.6mA
CP Clock input 1.0/1.0 20µA/0.6mA
74F825 CE Clock enable input (active low) 1.0/3.0 20µA/1.8mA
74F826 MR Master reset input (active low) 1.0/3.0 20µA/1.8mA
OE Output enable input (active low) 1.0/3.0 20µA/1.8mA
Qn, Qn Data outputs 1200/106.7 24mA/64mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOAD VALUE
HIGH/LOW
PIN CONFIGURATION – 74F821
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
D8
D9
11
GND
SF00482
LOGIC SYMBOL – 74F821
24
V
CC
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
Q9
14
1312
CP
13
= Pin 24
V
CC
GND = Pin 12
1
23456789
D0 D1 D2 D3 D4 D5 D6 D7
CP
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
23 22 21 20 19 18 17 16
10 11
D8 D9
Q8 Q9
15 14
SF00483
1996 Jan 05
3
Page 4
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
IEC/IEEE SYMBOL – 74F821
1
13
2
3
4
5
6
7
8
9
10
11
EN1
G2
2D
PIN CONFIGURATION – 74F822
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
D8
D9
11
GND
IEC/IEEE SYMBOL – 74F822
1
13
1
23
22
21
20
19
18
17
16
15
14
SF00484
2
3
4
5
6
7
8
9
10
11
EN1
G2
2D
1
23
22
21
20
19
18
17
16
15
14
SF00487
PIN CONFIGURATION – 74F823
24
V
CC
23
0
Q
22
Q
1
21
2
Q
20
3
Q
19
Q4
18
Q
5
17
Q
6
16
Q7
15
Q
8
9
Q
14
1312
CP
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
MR
GND
1
2
3
4
5
6
7
8
9
10
11
24
V
CC
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
CE
14
1312
CP
LOGIC SYMBOL – 74F822
23456789
D0 D1 D2 D3 D4 D5 D6 D7
CP
13
OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
= Pin 24
V
CC
GND = Pin 12
1996 Jan 05
23 22 21 20 19 18 17 16
SF00485
10 11
D8 D9
Q8 Q9
15 14
SF00486
LOGIC SYMBOL – 74F823
23456789
D0 D1 D2 D3 D4 D5 D6 D7
CP
13
CE
14
MR
11
OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
23 22 21 20 19 18 17 16
4
= Pin 24
V
CC
GND = Pin 12
SF00488
10
D8
Q8
15
SF00489
Page 5
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
IEC/IEEE SYMBOL – 74F823
1
11
14
13
2
3
4
5
6
7
8
9
10
EN1
R
G1
1G2
2D
PIN CONFIGURATION – 74F824
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
D8
MR
11
GND
IEC/IEEE SYMBOL – 74F824
1
11
14
13
1
23
22
21
20
19
18
17
16
15
SF00490
2
3
4
5
6
7
8
9
10
EN1
R
G1
2D
1G2
1
23
22
21
20
19
18
17
16
15
SF00493
PIN CONFIGURATION – 74F825
1
0
24
V
CC
23
0
Q
22
Q
1
21
2
Q
20
3
Q
19
Q4
18
5
Q
17
6
Q
16
Q7
15
Q
8
CE
14
1312
CP
OE
OE
DO
MR
GND
2
I
3
4
D1
5
D2
6
D3
7
D4
D5
8
D6
9
10
D7
11
24
V
CC
23
OE2
22
QO
21
Q1
20
Q2
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
CE
14
CP
1312
LOGIC SYMBOL – 74F824
23456789
D0 D1 D2 D3 D4 D5 D6 D7
CP
13
CE
14
MR
11
OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
= Pin 24
V
CC
GND = Pin 12
1996 Jan 05
23 22 21 20 19 18 17 16
SF00491
10
D8
Q8
15
SF00492
LOGIC SYMBOL – 74F825
13
CP
14
CE
11
MR
1
OE0
2
OE1
23
OE2
= Pin 24
V
CC
GND = Pin 12
5
SF00494
3456789
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
22 21 20 19 18 17 16
SF00495
10
15
Page 6
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
IEC/IEEE SYMBOL – 74F825
1
2
23
11
14
13
3
4
5
6
7
8
9
10
&
EN
R
G1
1G2
2D
PIN CONFIGURATION – 74F826
1
OE0
2
OE
I
3
DO
4
D1
5
D2
6
D3
7
D4
D5
8
D6
9
10
D7
11
MR
GND
LOGIC SYMBOL – 74F826
13
14
11
1
2
23
= Pin 24
1
2
23
11
14
13
3
4
5
6
7
8
9
10
V
OE
QO
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CE
CP
CC
22
21
20
19
18
17
16
15
SF00496
2
V
CC
GND = Pin 12
IEC/IEEE SYMBOL – 74F826
1
24
23
22
21
20
19
18
17
16
15
14
1312
3456789
D0 D1 D2 D3 D4 D5 D6 D7
CP
CE
MR
OE0
OE1
OE2
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
22 21 20 19 18 17 16
&
EN
R
G1
1G2
2D
1
10
15
SF00498
22
21
20
19
18
17
16
15
SF00499
LOGIC DIAGRAM FOR 74F821
13
CP
1
OE
VCC = Pin 24
GND = Pin 12
1996 Jan 05
D0
2
D
CP
D1
3
Q0
D
Q
CP
23
Q
D2
Q1
SF00497
4
22
D
CP
D3
5
Q2
D
CP
21
Q
D4
6
Q
20
Q3
D
CP
D5
7
D
Q
CP
19
Q4
D6
8
Q
18
Q5
D
CP
D7
9
D
Q
CP
17
Q6
D8
10
Q
16
Q7
D
CP
D9
11
D
Q
Q8
Q
CP
15
14
Q9
SF00500
6
Page 7
Philips Semiconductors Product specification
INPUTS
Load and read data
74F821/822/823/824/825/826Bus interface registers
LOGIC DIAGRAM FOR 74F822
13
CP
1
OE
VCC = Pin 24
GND = Pin 12
D0
2
D
CP
D1
3
Q
D
CP
23
Q0
D2
4
Q
D
CP
22
1
Q
D3
5
Q
D
CP
21
2
Q
D4
6
Q
D
CP
20
3
Q
D5
7
D
Q
CP
19
4
Q
D6
8
Q
D
Q
CP
18
5
Q
FUNCTION TABLE FOR 74F821 AND 74F822
OUTPUTS
74F821 74F822
OE CP Dn Q Q
L ↑ l L H
L ↑ h H L
L ↑ X NC NC Hold
H X X Z Z High impedance
H = High-voltage level
h = High state must be present one setup time before the low-to-high clock transition
L = Low-voltage level
l = Low state must be present one setup time before the low-to-high clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-high clock transition
= Not low-to-high clock transition
↑
D7
9
D
CP
17
6
Q
D8
10
Q
D
CP
16
7
Q
D9
11
D
Q
Q
Q
CP
15
8
14
Q9
SF00501
OPERATING MODE
LOGIC DIAGRAM FOR 74F823
CE
CP
V
CC
GND = Pin 12
1996 Jan 05
14
13
= Pin 24
MR
OE
CP
D1
3
Q0
D
R
23
Q
D0
2
D
R
11
1
CP
D2
4
Q1
D
R
22
Q
CP
D3
5
Q2
D
R
21
Q
CP
D4
6
Q3
D
R
20
Q
CP
D5
7
D
Q
R
19
Q4
CP
D6
8
Q
18
Q5
D7
9
CP
D
R
D
Q
R
17
Q6
CP
D8
10
CP
D
16
R
SF00502A
Q
15
Q8
Q
Q7
7
Page 8
Philips Semiconductors Product specification
INPUTS
Load and read data
74F821/822/823/824/825/826Bus interface registers
LOGIC DIAGRAM FOR 74F824
14
CE
13
CP
VCC = Pin 24
GND = Pin 12
MR
OE
CP
D1
3
Q
D
23
Q0
D0
2
D
R
11
1
D2
4
CP
Q
R
D
R
22
Q
1
CP
D3
5
Q
D
R
21
Q
2
CP
D4
6
Q
20
Q
3
D5
7
CP
D
Q
R
D
R
19
Q
4
CP
D6
8
Q
D
R
18
Q
5
FUNCTION TABLE for 74F823 and 74F824
OUTPUTS
74F823 74F824
OE MR CE* CP Dn Q Q
L L X X X L L Clear
L H L ↑ h H L
L H L ↑ l L H
L H H X X NC NC Hold
H X X X X Z Z High impedance
H = High-voltage level
h = High state must be present one setup time before the low-to-high clock transition
L = Low-voltage level
l = Low state must be present one setup time before the low-to-high clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
* = Since CE
or other potentially glitch prone device on the CE
↑ = Low-to-high clock transition
input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders
input.
D7
9
CP
Q
17
Q
6
OPERATING MODE
D8
10
CP
D
Q
R
CP
D
Q
R
16
Q
7
15
8
Q
SF00503A
LOGIC DIAGRAM FOR 74F825
VCC = Pin 24
GND = Pin 12
1996 Jan 05
CE
CP
14
13
MR
OE
OE1
OE
D0
3
D
11
1
0
2
23
2
D1
4
CP
Q
R
Q0
D
R
22
CP
D2
5
Q1
D
R
21
Q
CP
D3
6
Q2
D
R
20
Q
CP
D4
7
Q
19
Q3
D5
8
CP
D
R
D
Q
R
18
Q4
CP
D6
9
Q
17
Q5
D7
10
CP
D
Q
R
Q6
CP
D
Q
R
16
15
Q7
SF00504A
8
Page 9
Philips Semiconductors Product specification
INPUTS
Load and read data
T
Operating free-air temperature range
74F821/822/823/824/825/826Bus interface registers
LOGIC DIAGRAM FOR 74F826
D0
CE
CP
V
= Pin 24
CC
GND = Pin 12
14
13
11
MR
1
OE
0
2
OE
1
23
2
OE
3
D
R
FUNCTION TABLE FOR 74F825 AND 74F826
OEn MR CE* CP Dn Q Q
L L X X X L L Clear
L H L ↑ h H L
L H L ↑ l L H
L H H X X NC NC Hold
H X X X X Z Z High impedance
H = High-voltage level
h = High state must be present one setup time before the low-to-high clock transition
L = Low-voltage level
l = Low state must be present one setup time before the low-to-high clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
* = Since CE
or other potentially glitch prone device on the CE
↑ = Low-to-high clock transition
input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders
CP
D1
4
Q
D
R
22
Q0
CP
D2
5
D
Q
R
21
1
Q
CP
D3
6
Q
D
20
2
Q
D4
7
CP
Q
R
19
3
Q
D5
8
CP
D
R
D
Q
R
18
4
Q
CP
D6
9
Q
17
5
Q
D7
10
CP
D
Q
R
CP
D
Q
R
16
6
Q
Q
SF00505A
15
7
OUTPUTS
74F825 74F826
OPERATING MODE
input.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
amb
T
stg
1996 Jan 05
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in high output state –0.5 to V
Current applied to output in low output state 128 mA
p
Storage temperature range –65 to +150 °C
PARAMETER RATING UNIT
CC
p
Commercial range 0 to +70 °C
Industrial range –40 to +85 °C
V
9
Page 10
Philips Semiconductors Product specification
SYMBOL
UNIT
T
O erating free-air tem erature range
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
I
15mA
VOHHigh-level output voltage
V
MAX
I
24mA
VOLLow-level output voltage
V
MAX
I
MAX
74F822
74F824
74F826
74F821/822/823/824/825/826Bus interface registers
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN NOM MAX
V
V
V
I
I
I
CC
IH
IL
Ik
OH
OL
amb
Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
Input clamp current –18 mA
High–level output current –24 mA
Low–level output current 64 mA
p
p
Commercial range 0 +70 °C
Industrial range –40 +85 °C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
= –
VCC = MIN,
p
=
IL
VIH = MIN
OH
,
= –
OH
VCC = MIN,
=
= MIN
,
=
OL
IK
= 2.7V 50 µA
O
V
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
p
IK
Input clamp voltage VCC = MIN, II = I
IL
V
IH
Input current at maximum input voltage VCC = 0.0V, VI = 7.0V 100 µA
High–level input current VCC = MAX, VI = 2.7V 20 µA
Low–level input current VCC = MAX, VI = 0.5V –20 µA
Off–state output current, high–level voltage applied VCC = MAX, V
Off–state output current, low–level voltage applied VCC = MAX, VO = 0.5V –50 µA
Short–circuit output current
Supply current (total)
3
74F821,
74F823,
74F825,
VCC = MAX -100 -225 mA
I
CCH
VCC = MAX
I
CCL
I
CCZ
I
CCH
VCC = MAX
I
CCL
I
CCZ
I
CCH
VCC = MAX
I
CCL
I
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
= 5V, T
CC
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
amb
= 25°C.
, the use of high-speed test apparatus and/or sample-and-hold
OS
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
tests should be performed last.
OS
±10%V
±5%V
±10%V
±5%V
±10%V
±5%V
LIMITS
LIMITS
MIN TYP2MAX
2.4 V
CC
2.4 V
CC
2.0 V
CC
2.0 V
CC
CC
CC
0.42 0.55 V
–0.73 –1.2 V
75 105 mA
75 105 mA
75 115 mA
65 100 mA
70 105 mA
75 110 mA
60 85 mA
60 90 mA
65 95 mA
0.55 V
1996 Jan 05
10
Page 11
Philips Semiconductors Product specification
74F826
74F821/822/823/824/825/826Bus interface registers
AC ELECTRICAL CHARACTERISTICS FOR 74F821/74F822/74F824/74F825/74F826
LIMITS
T
SYMBOL PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum clock frequency Waveform 1 150 180 140 ns
Propagation delay
CP to Qn or Qn
Propagation delay
CP to Qn
Propagation delay
MR to Qn or Qn
Output enable time
OEn to Qn or Qn
Output disable time
OEn to Qn or Qn
TEST
CONDITION
74F821,
74F825, 74F826
Waveform 1
74F822, 74F824 Waveform 1
74F824
74F825, 74F826
Waveform 2 3.0 5.0 8.0 3.0 8.0 ns
Waveform 4
Waveform 5
Waveform 4
Waveform 5
= +25°C
amb
VCC = +5.0V
C
= 50pF, RL = 500Ω
L
MIN TYP MAX MIN MAX
4.0
4.0
4.5
4.5
2.0
3.0
1.5
1.5
6.5
6.0
6.5
6.5
4.5
5.0
3.5
3.5
8.5
8.5
9.0
9.0
8.0
8.0
6.5
6.5
T
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
C
= 50pF, RL = 500Ω
L
4.0
3.5
4.5
10.0
4.5
2.0
2.5
1.5
1.5
9.5
9.0
9.0
9.0
9.0
7.5
7.5
UNIT
ns
ns
ns
ns
AC SETUP REQUIREMENTS FOR 74F821/74F822/74F824/74F825/74F826
T
= +25°C
SYMBOL PARAMETER
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(H)
w
t
(L)
w
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(L) MR Pulse width, low
w
t
rec
Setup time, high or low
Dn to CP
Hold time, high or low
Dn to CP
CP Pulse width,
high or low
Setup time, high or low,
CE to CP
Hold time, high or low
CE to CP
Recovery time, MR to CP Waveform 2 2.5 2.5 ns
74F824, 74F825,
74F826
TEST
CONDITION
Waveform 3
Waveform 3
Waveform 1
Waveform 3
Waveform 3
Waveform 2 4.5 4.5 ns
amb
VCC = +5.0V
C
= 50pF, RL = 500Ω
L
MIN TYP MAX MIN MAX
1.0
1.0
2.0
2.0
3.5
3.5
0.0
2.0
0.0
3.0
LIMITS
T
amb
VCC = +5.0V ± 10%
C
= 50pF, RL = 500Ω
L
1.0
1.0
2.0
2.0
4.0
4.0
0.0
2.0
0.0
3.5
= 0°C to +70°C
UNIT
ns
ns
ns
ns
ns
1996 Jan 05
11
Page 12
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
AC ELECTRICAL CHARACTERISTICS FOR 74F823
LIMITS
T
SYMBOL PARAMETER
f
max
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum clock frequency Waveform 1 150 180 140 130 ns
Propagation delay
CP to Qn or Qn
Propagation delay
MR to Qn or Qn
Output enable time
OE
n to Qn or Qn
Output disable time
OEn to Qn or Qn
TEST
CONDITION
Waveform 1
Waveform 2 3.0 5.0 8.0 3.0 8.0 3.0 8.5 ns
Waveform 4
Waveform 5
Waveform 4
Waveform 5
AC SETUP REQUIREMENTS FOR 74F823
SYMBOL PARAMETER
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(H)
w
t
(L)
w
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(L)
w
t
rec
Setup time, high or low
Dn to CP
Hold time, high or low
Dn to CP
CP Pulse width,
high or low
Setup time, high or low,
CE
to CP
Hold time, high or low
CE to CP
MR Pulse width,
low
Recovery time,
MR to CP
TEST
CONDITION
Waveform 3
Waveform 3
Waveform 1
Waveform 3
Waveform 3
Waveform 2 4.5 4.5 4.5 ns
Waveform 2 2.5 2.5 2.5 ns
= +25°C
amb
VCC = +5.0V
C
= 50pF
L
R
= 500Ω
L
MIN TYP MAX MIN MAX MIN MAX
4.0
6.5
4.0
6.0
2.0
4.5
3.0
5.0
1.5
3.5
1.5
3.5
T
= +25°C
amb
VCC = +5.0V
C
= 50pF
L
R
= 500Ω
L
MIN TYP MAX MIN MAX MIN MAX
1.0
1.0
2.0
2.0
3.5
3.5
0.0
2.0
0.0
3.0
T
amb
VCC = +5.0V ± 10%
8.5
8.5
8.0
8.0
6.5
6.5
4.0
3.5
2.0
2.5
1.5
1.5
T
amb
VCC = +5.0V ± 10%
1.0
1.0
2.0
2.0
4.0
4.0
0.0
2.0
0.0
3.5
= 0°C to +70°C
C
= 50pF
L
R
= 500Ω
L
9.5
9.0
9.0
9.0
7.5
7.5
LIMITS
= 0°C to +70°C
C
= 50pF
L
R
= 500Ω
L
T
= –40°C to +85°C
amb
VCC = +5.0V ± 10%
C
= 50pF
L
R
= 500Ω
L
4.0
3.5
2.0
2.5
1.5
1.5
T
= –40°C to +85°C
amb
VCC = +5.0V ± 10%
C
= 50pF
L
R
= 500Ω
L
2.0
1.5
2.5
2.0
4.0
4.0
0.0
2.0
1.5
4.0
10.0
9.0
11.0
9.0
8.5
8.5
UNIT
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
1996 Jan 05
12
Page 13
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
max
CP
V
M
Qn
Qn
t
PLH
t
PHL
tw(H)
V
M
tw(L)
V
M
V
M
V
t
t
PLH
M
PHL
V
M
V
M
SF00506
Waveform 1. Propagation delay for clock input to output,
clock pulse width, and maximum clock frequency
Waveform 2. Master reset pulse width, master reset to output
MR
CP
Qn, Qn
V
M
t
PHL
tw(L)
V
M
t
rec
V
M
V
M
SF00507
delay and master reset to clock recovery time
Dn, CE
CP
V
M
t
(H) th(H)
su
V
M
V
M
V
tsu(L) th(L)
V
M
V
M
M
SF00508
Waveform 3. Data setup time and hold times
OEn
Qn, Q
n
V
t
PZL
M
V
V
M
t
PLZ
M
VOL +0.3V
SF00510
Waveform 5. 3-State output enable time to low level and
output disable time from low level
3.5V
OEn
Qn, Qn
V
t
PZH
M
V
M
t
PHZ
V
M
VOH -0.3V
0V
SF00509
Waveform 4. 3-State output enable time to high level and
output disable time from high level
1996 Jan 05
13
Page 14
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
TEST CIRCUIT AND WAVEFORMS
V
CC
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
Test Circuit for Open Collector Outputs
SWITCH POSITION
TEST SWITCH
t
t
PLZ
PZL
closed
closed
All other open
7.0V
R
L
C
R
L
L
NEGATIVE
PULSE
POSITIVE
PULSE
90%
10%
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
Input Pulse Definition
t
w
V
M
10%
)
)
t
)
TLH (tr
t
)
THL (tf
90%
V
M
t
w
90%
10%
AMP (V)
0V
AMP (V)
0V
DEFINITIONS:
= Load resistor;
R
L
see AC electrical characteristics for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
family
74F
INPUT PULSE REQUIREMENTS
V
amplitude
3.0V
M
1.5V
rep. rate
1MHz 500ns
t
w
t
TLHtTHL
2.5ns 2.5ns
SF00128
1996 Jan 05
14
Page 15
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1
1996 Jan 05
15
Page 16
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
1996 Jan 05
16
Page 17
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
NOTES
1996 Jan 05
17
Page 18
Philips Semiconductors Product specification
74F821/822/823/824/825/826Bus interface registers
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
(print code) Date of release: July 1994
Document order number: 9397-750-05185
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