Datasheet 74f776 DATASHEETS (Philips)

Page 1
INTEGRATED CIRCUITS
74F776
Pi-bus transceiver
Product specification IC15 Data Handbook
 
1990 Dec 19
Page 2
74F776Pi–bus transceiver

FEA TURES

• Octal latched transceiver
• Drives heavily loaded backplanes with equivalent load impedances
down to 10 ohms
• High drive (100mA) open collector drivers on B port
• Reduced voltage swing (1 volt) produces less noise and reduces
power consumption
• High speed operation enhances performance of backplane buses and facilitates incident wave switching
• Compatible with Pi–bus and IEEE 896 Futurebus standards
• Built–in precision band–gap reference provides accurate receiver
thresholds and improved noise immunity
• Controlled output ramp and multiple GND pins minimize ground bounce
• Glitch–free power up/power down operation
• Multiple package options
• Industrial temperature range available (–40°C to +85°C)

DESCRIPTION

The 74F776 is an octal bidirectional latched transceiver and is intended to provide the electrical interface to a high performance wired–OR bus. The B port inverting drivers are low–capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 100 mV threshold region and a 4ns glitch filter.
The 74F776 B port interfaces to ’Backplane Transceiver Logic’ (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power
consumption and a series diode on the drivers to reduce capacitive loading. Incident wave switching is employed, therefore BTL propagation delays are short. Although the voltage swing is less for BTL, so is its receiver threshold, therefore noise margins are excellent.
BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane.
The 74F776 A port has TTL 3–state drivers and TTL receivers with a latch function. A separate high–level control voltage input (V provided to limit the A side output level to a given voltage level (such as 3.3V). For 5.0V systems, V
The 74F776 has a designed feature to control the B output transitions during power sequencing. There are two possible sequencing, They are as follows:
1.When LE the LE making a maximum of one transition during power–up (or down).
2. If LE = high or OEBn = high then the B outputs will be disabled during power–up (or down).
= low and OEBn = low then the B outputs are disabled until
circuitry takes control. Then the B outputs will follow the A inputs,
TYPE
74F776 6.5ns 80mA
TYPICAL PROPAGA-
TION DELAY
is simply tied to VCC.
X
TYPICAL SUPPL Y
CURRENT( TOTAL)
) is
X

ORDERING INFORMATION

ORDER CODE
COMMERCIAL RANGE INDUSTRIAL RANGE
DESCRIPTION
28–pin plastic DIP (600 mil) N74F776N I74F776N SOT117-2
28–pin PLCC N74F776A I74F776A SOT261-2
VCC = 5V ±10%, T
= 0°C to +70°C VCC = 5V ±10%, T
amb
= –40°C to +85°C
amb
PKG DWG #

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS DESCRIPTION
A0 – A7 PNP latched inputs 3.5/0.1 17 70µA/70µA B0 – B7 Data inputs with threshold circuitry 5.0/0.167 100µA/100µA
OEA A output enable input (active high) 1.0/0.033 20µA/20µA
OEB0, OEB1 B output enable inputs (active low) 1.0/0.033 20µA/20µA
LE Latch enable input (active low) 1.0/0.033 20µA/20µA A0 – A7 3–state outputs 150/40 3mA/24mA B0 – B7 Open collector outputs OC/166.7 OC/100mA
Notes to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. OC = Open collector.
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
December 19, 1990 853 1121 01321
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Philips Semiconductors Product specification
74F776Pi–bus transceiver

PIN CONFIGURATION

1
V
CC
2
OEA
3
A0
4
GND
5
A1
6
A2
7
A3
8
GND
9
A4
10 19
A5
GND
11
A6
12
A7
13
VX
14 15
PIN CONFIGURA TION PLCC
V
OEAA0GND LE B0 B1
CC
PLCC
A7A6 OEB1
V
X
GND
GND
4 3 2 1 28 27
5
A1
6
A2
7
A3
8 9
A4 A5
10 11
12
16 17151413
28 27 26 25 24 23 22 21 20
18 17 16
SF00422
B7
LE B0 B1 GND B2 B3 GND B4 B5 B6 GND B7 OEB OEB
26
18 GNDOEB0
1 0
25
GND
24
B2 B3
23 22
GND
21
B4
20
B5
19
B6
SF00423

IEC/IEEE SYMBOL

15 16 28 2
3
5 6 7 9 10 12 13

LOGIC SYMBOL

15
OEB0
2
OEA
28
LE
16
OEB1
VCC = Pin 1, V GND = Pin 4, 8, 11, 18, 22, 25
= Pin 14
X
&
EN2
EN1 EN3
ID
2
3
35679101213
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
27 26 24 23 21 20 19 17
27
26 24 23 21 20 19 17
SF00425
SF00424

PIN DESCRIPTION

SYMBOL PINS TYPE NAME AND FUNCTION
A0 – A7 3, 5, 6, 7, 9, 10, 12, 13 I/O PNP latched input/3–state output (with VX control option) B0 – B7 27, 26, 24, 23, 21, 20, 19, 17 I/O
OEB0 15 Input Enables the B outputs when both pins are low OEB1 16 Input
OEA 2 Input Enables the A outputs when high
LE 28 Input Latched when high (a special feature is built in for proper enabling times) V
X
14 Input Clamping voltage keeping VOH from rising above VX (VX = Vcc for normal use)
December 19, 1990
Data input with special threshold circuitry to reject noise/ open collector output, high current drive
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Philips Semiconductors Product specification
74F776Pi–bus transceiver

LOGIC DIAGRAM

15
OEB0
16
OEB
1
2
OEA
28
LE
A0
3
Data
LE
Q
27
B0
A1
A2
A3
A4
A5
A6
A7
5
6
7
9
10
12
13
Data
LE
Data
LE
Data
LE
Data
LE
Data
LE
Data
LE
Data
LE
Q
Q
Q
Q
Q
Q
Q
26
B1
24
B2
23
B3
21
B4
20
B5
19
B6
17
B7
= Pin 1, V
V
CC
GND = Pin 4, 8, 11, 18, 22, 25
= Pin 14,
X
December 19, 1990
SF00426
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Philips Semiconductors Product specification
74F776Pi–bus transceiver

FUNCTION TABLE

INPUTS LATCH OUTPUTS OPERATING MODE
An Bn* LE OEA OEB0 OEB1 STATE An Bn
H X L L L L H Z Z A 3–state, data from A to B
L X L L L L L Z L
X X H L L L Qn Z Qn A 3–state, latched data to B
– – L H L L (1) (1) (1) Feedback: A to B, B to A – H H H L L H (2) H Z(2) Preconditioned latch enabling data transfer from B to A – L H H L L H (2) L Z(2) – – H H L L Qn Qn Qn Latch state to A and B
H X L L H X H Z Z
L X L L H X L Z Z B and A 3–state
X X H L H X Qn Z Z
– H L H H X H H Z – L L H H X L L Z B 3–state, data from B to A – H H H H X Qn H Z – L H H H X Qn L Z
H X L L X H H Z Z
L X L L X H L Z Z B and A 3–state
X X H L X H Qn Z Z
– H L H X H H H Z – L L H X H L L Z B 3–state, data from B to A – H H H X H Qn H Z – L H H X H Qn L Z
Notes to function table
H = High voltage level L = Low voltage level X = Don’t care – = Input not externally driven Z = High impedance ”off” state Q
= High or Low voltage level one setup time prior to the low–to–high LE transition.
n
(1) = Condition will cause a feedback loop path: A to B and B to A. (2) = The latch must be preconditioned such that B inputs may assume a high or low level while OEB B* = Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.
0 and OEB1 are low and LE is high.
December 19, 1990
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Philips Semiconductors Product specification
range
74F776Pi–bus transceiver

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
V
CC
V
X
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage –0.5 to +7.0 V Threshold control –0.5 to +7.0 V Input voltage OEBn, OEA, LE –0.5 to +7.0 V
Input current –40 to +5 mA Voltage applied to output in high output state –0.5 to V
Current applied to output in low output state A0 – A7 48 mA
Operating free air temperature range Commercial range 0 to +70
Storage temperature range –65 to +150
PARAMETER RATING UNIT
A0 – A7, B0 – B7 –0.5 to +5.5 V
CC
V
B0 – B7 200 mA
°C
Industrial range –40 to +85
°C °C

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT
MIN NOM MAX
V V
V
I
I I
T
CC IH
IL
Ik
OH OL
amb
Supply voltage 4.5 5.0 5.5 V High–level input voltage Except B0 – B7 2.0 V
B0 – B7 1.6 V
Low–level input voltage Except B0 – B7 0.8 V
B0 – B7 1.45 V
Input clamp current Except A0 – A7 –18 mA
A0 – A7 –40 mA High–level output current A0 – A7 –3 mA Low–level output current A0 – A7 24 mA
B0 – B7 100 mA Operating free air temperature
range
Commercial range 0 +70
Industrial range –40 +85
°C °C
December 19, 1990
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Philips Semiconductors Product specification
74F776Pi–bus transceiver

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
I I
V
V
V
I
OH OFF
OH
OL
IK
I
High–level output current B0 – B7 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA Power–off output current B0 – B7 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA
High-level output voltage A0 – A7
Low-level output voltage B0 – B7 VIL = MAX I
Input clamp voltage A0 – A7 VCC = MIN, II = I
Input current at OEBn, OEA, LE VCC = 0.0V, VI = 7.0V 100 µA maximum input voltage A0 – A7, B0 – B7 VCC = MAX, VI = 5.5V 1 mA
I
IH
I
IL
I
OZH
I
OZL
I
X
I
OS
I
CC
High–level input current OEBn, OEA, LE VCC = MAX, VI = 2.7V, Bn –An =0V 20 µA
Low–level input current OEBn, OEA, LE VCC = MAX, VI = 0.5V –20 µA
Off state output current,
+ I
IH
high level voltage applied Off state output current,
+ I
IL
low level voltage applied
High–level control current
Short circuit output
3
current
Supply current (total) I
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. Unless otherwise specified, V
2. All typical values are at VCC = 5V, T
3. Not more than one output should be shorted at a time. For testing I techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I
4. Due to test equipment limitations, actual test conditions are for V
PARAMETER TEST LIMITS UNIT
1
= –3mA, VX =V
OH
I
= –4mA,
OH
VX =3.13V and 3.47V
= 20mA, VX = V
OL
= 100mA 1.15 V
OL
= 4mA 0.40 V
OL
MIN TYP2MAX
2.5 V
CC
2.5 V
CC
CC
0.50 V
-0.5 V
-1.2 V
V
VCC = MIN, I
4
VIL = MAX, VIH = MIN
4
A0 – A7
VCC = MIN, I
VIH = MIN I
Except A0 – A7 VCC = MIN, II = I
CONDITIONS
IK IK
B0 – B7 VCC = MAX, VI = 2.1V 100 µA
B0 – B7 VCC = MAX, VI = 0.3V –100 µA A0 – A7 VCC = MAX, V
A0 – A7 VCC = MAX, VO = 0.5V –70
A0 – A7 only
I
CCH CCL
I
CCZ
= VCC for all test conditions.
X
OS
= 25°C.
amb
tests should be performed last.
= 2.7V 70
O
VCC = MAX, V
2.7V, A0 – A7 = 2.7V, B0 – B7 = 2.0V, VCC = MAX, V
2.7V, OEBn = A0 – A7 = 2.7V, B0 – B7 = 2.0V, VCC = MAX, Bn = 1.8V, OEA = 2.0V,
OEBn = 2.7V
= VCC, LE = OEA = OEBn =
X
= 3.13 & 3.47V , LE = OEA =
X
–100 100 µA
–10 10 µA
-60 -150 mA
VCC = MAX 65 100 mA VCC = MAX, VIL = 0.5V 100 145 mA
75 100 mA
, the use of high-speed test apparatus and/or sample-and-hold
OS
=1.8v and VIL = 1.3V.
IH
µA
µA
December 19, 1990
7
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Philips Semiconductors Product specification
74F776Pi–bus transceiver

AC ELECTRICAL CHARACTERISTICS

A PORT LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V
CONDITION CL = 50pF,
RL = 500Ω
MIN TYP MAX MIN MAX MIN MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay Bn to An
Output enable time to high or low, OEA to An
Output disable time from high or low, OEA to An
Waveform 1
Waveform 3, 4
Waveform 3, 4
5.5
8.0
4.5
6.0
8.0
10.5
8.5
11.0
2.0
3.5
2.0
4.5
T
= +25°C T
amb
TEST
SYMBOL PARAMETER CONDITION VCC = +5.0V
C
= 30pF, RU = 9Ω CD = 30pF, RU = 9Ω CD = 30pF, RU = 9Ω
D
MIN TYP MAX MIN MAX MIN MAX
t t
t t
t t
t t
PLH PHL
PLH PHL
PLH PHL
TLH THL
Propagation delay An to Bn
Propagation delay LE to Bn
Enable/disable time OEB
n to An
Transition time, B port
1.3V to 1.7V , 1.7V to 1.3V
Waveform 1
Waveform 1
Waveform 1
Test Circuit and
Waveforms
3.0
3.0
3.5
3.5
3.0
3.5
0.5
0.5
5.0
4.5
5.0
5.0
4.5
5.5
2.0
2.0
12.0
9.0
13.5
13.5
6.0
7.0
7.0
7.5
8.0
8.0
7.0
9.0
4.5
4.5
= 0°C to
amb
+70
VCC = +5.0V ± 10% VCC = +5.0V ± 10%
°C
CL = 50pF,
RL = 500Ω
5.5
4.5
7.5
8.0
1.5
2.0
12.0
9.0
15.0
15.5
6.5
7.5
T
= –40°C to +85°C
amb
CL = 50pF,
RL = 500Ω
5.5
4.5
7.5
8.0
1.5
2.0
12.0
9.0
15.5
15.5
6.5
7.5
B PORT LIMITS
amb
+70
= 0°C to
°C
T
= –40°C to +85°C
amb
VCC = +5.0V ± 10% VCC = +5.0V ± 10%
2.5
2.5
3.0
2.5
2.5
3.5
0.5
0.5
8.0
8.5
9.0
9.0
8.0
10.0
5.0
4.5
2.0
2.5
2.5
2.5
2.5
3.5
0.5
0.5
9.0
8.5
9.5
9.5
8.5
10.5
5.0
4.5
UNIT
ns
ns
ns
UNIT
ns
ns
ns
ns

AC SETUP REQUIREMENTS

LIMITS
T
TEST
= +25°C T
amb
SYMBOL PARAMETER CONDITION VCC = +5.0V
CL = 50pF,
RL = 500Ω
= 0°C to +70°C T
amb
= –40°C to +85°C
amb
VCC = +5.0V ± 10% VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
CL = 50pF,
RL = 500Ω
MIN TYP MAX MIN MAX MIN MAX
t
(H)
su
t
(L)
su
th(H) t
(L)
h
t
(L) LE pulse width, low Waveform 2 4.0 5.0 5.0 ns
w
Setup time, high or low An to LE
Hold time, high or low An to LE
Waveform 2
Waveform 2
3.5
4.5
0.0
0.0
4.5
5.0
0.0
0.0
4.5
5.0
0.0
0.0

AC WAVEFORMS

An, Bn, OEB
An, Bn
n
V
M
t
PLH
Waveform 1. Propagation delay for data to output
V
M
t
PHL
V
M
V
M
SF00427
An
LE
V
M
tsu(L)
V
M
th(L) th(H)
V
M
V
M
V
tw(L)
M
ts(H)
V
Waveform 2. Data setup and hold times and LE pulse width
M
V
M
SF00428
UNIT
ns
ns
December 19, 1990
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Philips Semiconductors Product specification
74F776Pi–bus transceiver
AC WAVEFORMS (Continued)
OEA
An
V
M
t
PZH
V
M
t
PHZ
V
M
VOH -0.3V
0V
SF00429
Waveform 3. 3-state output enable time to high level and output disable time from high level
OEA
An
Waveform 4. 3-state output enable time to low level and output disable time from low level
Notes to AC waveforms
For all waveforms, V The shaded areas indicate when the input is permitted to change for predictable output performance.
= 1.5V.
M

TEST CIRCUIT AND WAVEFORMS

SWITCH POSITION
TEST SWITCH
, t
t
PLZ
PZL
closed
V
CC
openAll other
V
PULSE
GENERATOR
IN
R
D.U.T.
T
Test circuit for 3–State outputs on A port
V
CC
V
PULSE
GENERATOR
IN
R
D.U.T.
T
V
V
OUT
OUT
NEGATIVE PULSE
7.0V
R
L
C
R
L
L
7.0V
R
U
POSITIVE PULSE
family
A port
C
D
90%
10%
amplitude
3.0V
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
Input pulse definition
INPUT PULSE REQUIREMENTS
Low V
0.0V
1.0V
V
M
t
PZL
)
)
V
1.5V
V
M
t
w
10%
t
)
TLH (tr
t
)
THL (tf
90%
t
w
rep. rate
M
1MHz 500ns 2.5ns 1MHz 500nsB port 2.0V 1.0V
V
M
t
PLZ
VOL +0.3V
SF00430
AMP (V)
90%
V
M
low V
AMP (V)
V
M
10%
low V
t
t
TLHtTHL
w
2.5ns
4.0ns
4.0ns
Test circuit for outputs on B port
DEFINITIONS:
= Load resistor; see AC electrical characteristics for value.
R
L
CL= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RU= Pull up resistor; see AC electrical characteristics for value. C
= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
D
RT= Termination resistance should be equal to Z
December 19, 1990
of pulse generators.
OUT
9
SF00431
Page 10
Philips Semiconductors Product specification
74F776Pi-bus transceiver

DIP28: plastic dual in-line package; 28 leads (600 mil); long body SOT117-2

1990 Dec 19
10
Page 11
Philips Semiconductors Product specification
74F776Pi-bus transceiver

PLCC28: plastic leaded chip carrier; 28 leads SOT261-2

1990 Dec 19
11
Page 12
Philips Semiconductors Product specification
74F776Pi-bus transceiver

Data sheet status

Data sheet status
Objective specification
Preliminary specification
Product specification
Product status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98 Document order number: 9397-750-05177
 
yyyy mmm dd
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