Datasheet 74f674 DATASHEETS (Philips)

Philips Semiconductors Product specification

SI/O

74F67416-bit serial/parallel-in, serial-out shift register (3-State)

FEA TURES

•16-bit serial I/O shift register

•16-bit parallel-in/serial-out converter

•Recirculating serial shifting

•Common serial data I/O pin (3-State)

DESCRIPTION

The 74F674 is a 16-bit shift register with serial and parallel load capability and serial output. A single pin serves alternately as an input for serial entry or as a 3-State serial output. In the serial out mode the data recirculates in the register. Chip Select, Read/Write and Mode inputs provide control flexibility. The 74F674 operates in one of four modes, as indicated in the Function table.

Hold: A High signal on the Chip Select (CS and forces the Serial Input/Output (SI/O) 3-State buffer into the high impedance state.

Serial load: Data present on the SI/O pin shifts into the register on the falling edge of CP

. Data enters the Q0 position and shifts toward

Q15 on successive clocks. Serial output: The SI/O 3-State buffer is active and the register

contents are shifted out from Q15 and simultaneously shifted back into Q0.

Parallel load: Data present on D0–D15 is entered into the register on the falling edge of CP

. The SI/O 3-State buffer is active and represents the Q15 output. To prevent false clocking, CP Low during a Low-to-High transition of CS

) input prevents clocking

must be

.

PIN CONFIGURA TION

CS CP

2

R/W

3

NC

4 5

M

SI/O

6 7

D0 D1

8

D2

9

10 15

D3

D4

11 12 13

GND

TYPE TYPICAL f

MAX

74F674 95MHz 55mA

V

241

CC

D15

23 22

D14

21

D13

20

D12 D11

19 18

D10

17

D9

16

D8 D7

14

D6 D5

TYPICAL SUPPL Y

CURRENT

ORDERING INFORMATION

DESCRIPTION COMMERCIAL RANGE

24-Pin Plastic Slim DIP (300mil)

24-Pin Plastic SOL N74F674D

= 5V ±10%, T

V

CC

amb

N74F674N

SF01188

(TOTAL)

= 0°C to +70°C

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

74F(U.L.)

HIGH/LOW

D0–D15 Parallel data inputs 1.0/1.0 20µA/0.6mA CS Chip Select input (active Low) 1.0/1.0 20µA/0.6mA CP Clock Pulse input (active falling edge) 1.0/1.0 20µA/0.6mA M Mode select input 1.0/1.0 20µA/0.6mA R/W Read/Write input 1.0/1.0 20µA/0.6mA

Serial data input or 3.5/1.0 70mA/0.6mA Serial 3-state output 150/40 3.0mA/24mA

NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.

1989 Feb 05 853–1248 92263

1

LOAD VALUE

HIGH/LOW

Philips Semiconductors Product specification

SI/O

OPERATING

74F67416-bit serial/parallel-in, serial-out shift register (3-State)

LOGIC SYMBOL

D0 D1 D4 D5 D6 D7D3D2

1

CS

2

CP

3

R/W

5

M

V

= Pin 24

CC

GND = Pin 12

8910

11 13 147 16 17 18

D8 D9 D12 D13 D14 D15D11D10

SO

6

19 20 21 2215 23

FUNCTION TABLE

CONTROL INPUTS

CS R/W M CP

H X X X High Z Hold

L L X ↓ Data in Serial load L H L ↓ Data out

L H H ↓ Active

H = High voltage level L = Low voltage level X = Don’t care ↓ = High-to-Low transition of designed input

SI/O OPERATING

STATUS

Serial output with recirculation

Parallel load; no shifting

MODE

SF01189

LOGIC SYMBOL (IEEE/IEC)

5

3

1 2

7 8

9 10 11 13 14 15 16 17 18 19 20 21 22 23

0 1

&&EN

3, 4D 3, 4D

3, 4D

M

SRG16

0 3

C4(0/1/2)

, 4D

3

6

SF01190

LOGIC DIAGRAM

VCC= Pin 24 GND = Pin 12

CS

CP

R/W

D0–D15 (7–11, 13–23)

5

M

1

2

3

PE

Q0

CP

D0–D15

Q15

6

SI/O

SF01191

1989 Feb 05

2

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

1

UNIT

VOHHigh-l

VCC MIN, VIL MAX,

VOLL

VCC MIN, VIL MAX,

I

Input current at

SI/O

74F67416-bit serial/parallel-in, serial-out shift register (3-State)

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

V V I

IN

V I

OUT

T T

CC IN

OUT

amb stg

Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5.0 mA Voltage applied to output in High output state –0.5 to +V Current applied to output in Low output state 48 mA Operating free-air temperature range 0 to +70 °C Storage temperature –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

V V V I I I T

CC IH

IL IK OH OL

amb

Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V Low-level input voltage 0.8 V Input clamp current –18 mA High-level output current –3 mA Low-level output current 24 mA Operating free-air temperature range 0 70 °C

PARAMETER RATING UNIT

CC

V

LIMITS

MIN NOM MAX

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

V

IK

I

IH

I

IL

I

OZH+IIH

I

OZL+IIL

I

OS

I

CC

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value under the recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I

1989 Feb 05

LIMITS

MIN TYP

2

MAX

2.4 V

2.7 3.3 V

0.35 0.50 V

–0.73 –1.2 V

evel output voltage

ow-level output voltage

VCC = MIN, VIL = MAX,

VIH = MIN, I

OH

= MAX

VCC = MIN, VIL = MAX,

VIH = MIN, I

OL

= MAX Input clamp voltage VCC = MIN, II = I Input current at

maximum input voltage

SI/O only VCC = MAX, VI = 5.5V 100 µA others VCC = MAX, VI = 7.0V 100 µA

IK

1

±10%V

±5%V

±10%V

±5%V

CC

High-level input current VCC = MAX, VI = 2.7V 20 µA Low-level input current VCC = MAX, VI = 0.5V –0.6 mA Off-state output current

High-level voltage applied Off-state output current

Low-level voltage applied Short-circuit output current

SI/O only

3

VCC = MAX, VO = 2.7V 70 µA

V

= MAX, VO = 0.5V –600 µA

CC

VCC = MAX –60 –150 mA

Supply current (total) VCC = MAX 55 80 mA

= 5V, T

CC

OS

= 25°C.

amb

should be performed last.

, the use of high-speed test apparatus and/or sample-and-hold

OS

3

Philips Semiconductors Product specification

TEST

CONDITIONS

74F67416-bit serial/parallel-in, serial-out shift register (3-State)

AC ELECTRICAL CHARACTERISTICS

LIMITS

T

SYMBOL PARAMETER

f

MAX

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

PZH

t

PZL

t

PHZ

t

PLZ

Maximum clock frequency Waveform 1 80 95 70 MHz Propagation delay

to SI/O

CP Output Enable time

to SI/O

CS Output Disable time

to SI/O

CS Output Enable time

to SI/O

R/W Output Disable time

to SI/O

R/W

CONDITIONS

Waveform 1 Waveform 3

Waveform 4 Waveform 3

Waveform 4

= +25°C T

amb

VCC = +5.0V VCC = +5.0V ± 10%

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

7.0

6.0

5.5

7.0

3.0

4.5

6.0

7.5

5.0

5.5

9.5

8.5

9.5

6.0

7.5

8.5

10.0

7.5

8.0

12.5

11.5

11.0

12.5

8.5

10.0

11.5

13.0

10.5

11.0

= 0°C to +70°C

amb

6.5

5.5

5.0

6.5

3.0

4.5

5.5

7.0

4.5

5.0

14.0

12.5

14.0

10.0

11.5

13.0

14.0

12.0

13.5

UNIT

ns ns

AC SETUP REQUIREMENTS

SYMBOL PARAMETER TEST CONDITION

ts(H)

(L)

t

s

th(H)

(L)

t

h

ts(H)

(L)

t

s

th(H)

(L)

t

h

ts(H)

(L)

t

s

th(H)

(L)

t

h

ts(L)

th(H) tw(H)

(L)

t

w

Setup time, High or Low SI/O to CP

Hold time, High or Low SI/O to CP

Setup time, High or Low Dn to CP

Hold time, High or Low Dn to CP

Setup time, High or Low M to CP

Hold time, High or Low M to CP

Setup time, Low

to CP

CS Hold time, High

to CP

CS CP Pulse width,

High or Low

Waveform 2

Waveform 2 8.0 9.0 ns

Waveform 2 0.0 0.0 ns

Waveform 1

LIMITS

T

= +25°C T

amb

= 0°C to +70°C

amb

VCC = +5.0V VCC = +5.0V ± 10%

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

2.0

1.5

1.0

3.0

4.0

2.0

5.5

0.0

3.5

4.5

2.5

2.0

1.0

3.0

4.0

2.5

6.0

1.0

4.0

5.0

UNIT

ns ns

1989 Feb 05

4

Philips Semiconductors Product specification

74F67416-bit serial/parallel-in, serial-out shift register (3-State)

AC WAVEFORMS

For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.

1/f

CP

SI/O

V

M

t

PLH

tW(L)

MAX

V

M

V

M

tW(H)

V

M

t

PHL

V

M

Dn, CS, M, R/W SI/O

CP

V

M

,

ts(H) ts(L)th(H) th(L)

M

V

M

VMV

M

V

M

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock Frequency

CS, R/W

SI/O

V

M

t

PZH

V

M

t

PHZ

V

M

Waveform 3. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

TEST CIRCUIT AND WAVEFORM

V

CC

R

V

PULSE

GENERATOR

IN

R

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t t

PLZ PZL

closed closed

All other open

T

D.U.T.

V

OUT

L

R

C

L

SF01192

VOH -0.3V

0V

SF01194

7.0V NEGATIVE

PULSE

POSITIVE PULSE

Waveform 2. Setup and Hold Times

CS, R/W

SI/O

V

M

t

PZL

V

M

t

PLZ

M

Waveform 4. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

t

90%

10%

V

M

10%

t

THL (tf

t

TLH (tr

90%

V

M

w

10%

)

t

w

t

TLH (tr

t

THL (tf

)

90%

V

M

V

M

10%

Input Pulse Definition

SF01193

V

+0.3V

OL

SF01195

AMP (V)

0V

AMP (V)

0V

DEFINITIONS:

= Load resistor;

R

L

= Load capacitance includes jig and probe capacitance;

C

L

= Termination resistance should be equal to Z

R

T

1989 Feb 05

see AC electrical characteristics for value. see AC electrical characteristics for value. pulse generators.

OUT

of

family

74F

5

INPUT PULSE REQUIREMENTS

V

amplitude

3.0V

M

1.5V

rep. rate

1MHz 500ns

t

w

t

TLHtTHL

2.5ns 2.5ns

SF00777