Datasheet 74F652SCX, 74F652SC, 74F652ASCX, 74F652ASC, 74F652SPC Datasheet (Fairchild Semiconductor)

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March 1988 Revised August 1999

74F651 • 74F652 Transceivers/Registers

General Description

These devices consis t of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA

) are pro-

vided to control the transceiver function.

Features

■ Independent registers for A and B buses

■ Multiplexed real-time and stored data

■ Choice of non-inverting and inverting data paths

74F651 inverting 74F652 non-inverting

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram

Order Number Package Number Package Description

74F651SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F651SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 74F652SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

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74F651 • 74F652

Logic Symbols

74F651

IEEE/IEC

74F651

74F652

IEEE/IEC

74F652

Unit Loading/Fan Out

Function Table

H = HIGH Voltage Level X = Immaterial

L = LOW Voltage Level



= LOW-to-HIGH Clock Transition

Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on eve ry LOW -t o-HIGH transition on th e c lock inputs.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

A0–A7, B0–B

A and B Inputs/ 1.0/1.0 20 µA/−0.6 mA

3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (48 mA) CPAB, CPBA Clock Inputs 1.0/1.0 20 µA/−0.6 mA SAB, SBA Select Inputs 1.0/1.0 20 µA/−0.6 mA OEAB, OEBA

Output Enable Inputs 1.0/1.0 20 µA/−0.6 mA

Inputs Inputs/Outputs (Note 1)

Operating Mode

OEAB OEBA

CPAB CPBA SAB SBA

thru A7B0 thru B

L H H or L H or L X X Input Input Isolation LH



X X Store A and B Data



H or L X X Input Not Specified Store A, Hold B



X X Input Output Store A in Both Registe rs

LXH or L



X X Not Specified Input Hold A, Store B



X X Output Input Store B in Both Registers L L X X X L Output Input Real-Time B Data to A Bus L L X H or L X H Store B Data to A Bus H H X X L X Input Output Real-Time A Data to B Bus H H H or L X H X Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and

Stored B Data to A Bus

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74F651 • 74F652

Functional Description

In the transceiver mode , data present a t the HIGH impe dance port may be sto red in either the A or B register or both.

The select (SAB, SBA) controls can multiplex stored and real-time.

The examples in Figure 1 de monstr ate the fo ur funda mental bus-management func tions that can be perfor med with the Octal bus transceivers and receivers.

Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inp uts (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer m od e, it i s a lso po ssi ble to sto re d ata without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this confi guration ea ch Output reinforces its Input. Thus when all other data sources to the two sets of bus lines a re in a HIGH impedance state , each set of bus lines will remain at its last state.

Note A: Real-Time

Transfer Bus B to Bus A

Note B: Real-Time

Tran sfer Bus A to Bus B

Note C: Storage Note D: Transfer Storage

Data to A or B

FIGURE 1.

OEAB OEBA

CPAB CPBA SAB SBA

LLXXXL

OEAB OEBA CPAB CPBA SAB SBA

HHXXLX

OEAB OEBA CPAB CPBA SAB SBA



XXX

LXX





OEAB OEBA CPAB CPBA SAB SBA

H L H or L H or L H X

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74F651 • 74F652

Logic Diagrams

74F652

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

74F651

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

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74F651 • 74F652

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 3: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

ESD Last Passing Voltage (Min) 4000V

Free Air Ambi ent Temperat ure 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins)

Output HIGH

10% V

2.0 V Min IOH = −15 mA (An, Bn)

Voltage

Output LOW

10% V

0.55 V Min IOL = 64 mA (An, Bn)

Voltage

Input HIGH

5.0 µAMax

VIN = 2.7V

Current (Non I/O Pins)

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

BVIT

Input HIGH Current

0.5 mA Max

VIN = 5.5V

Breakdown (I/O) (An, Bn)

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6 mA Max VIN = 0.5V (Non I/O Pins)

IIH + I

OZH

Output Leakage Current 70 µAMaxV

OUT

= 2.7V (An, Bn)

IIL + I

OZL

Output Leakage Current −650 µAMaxV

OUT

= 0.5V (An, Bn)

Output Short-Circuit Current −100 −225 mA Max V

OUT

= 0V

Bus Drainage Test 500 µA0.0VV

OUT

= 5.25V

CCH

Power Supply Current 105 135 mA Max VO = HIGH

CCL

Power Supply Current 118 150 mA Max VO = LOW

CCZ

Power Supply Current 115 150 mA Max VO = HIGH Z

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74F651 • 74F652

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Max Min Max Min Max

MAX

Max. Clock Frequency 90 75 90 MHz

PLH

Propagation Delay 2.0 7.0 2.0 8.5 2.0 8.0

PHL

Clock to Bus 2.0 8.0 2.0 9.5 2.0 9.0

PLH

Propagation Delay 2.0 8.5 1.0 9.0 2.0 9.0

PHL

Bus to Bus (74F651) 1.0 7.5 1.0 8.0 1.0 8.0

PLH

Propagation Delay 1.0 7.0 1.0 8.0 1.0 7.5

PHL

Bus to Bus (74F652) 1.0 6.5 1.0 8.0 1.0 7.0

PLH

Propagation Delay 2.0 8.5 2.0 11.0 2.0 9.5

PHL

SBA or SAB to A or B 2.0 8.0 2.0 10.0 2.0 9.0

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

Min Max Min Max Min Max

PZH

Enable Time 2.0 9.5 2.0 10.0 2.0 10.0 ns

PZL

*OEBA to A 2.0 12.0 2.0 10.0 2.0 12.5

PHZ

Disable Time 1.0 7.5 1.0 9.0 1.0 8.0

PLZ

*OEBA to A 2.0 8.5 1.0 9.0 2.0 9.0

PZH

Enable Time 2.0 9.5 2.0 10.0 2.0 10.0

PZL

OEAB to B 3.0 13.0 2.0 12.0 3.0 14.0

PHZ

Disable Time 2.0 9.0 1.0 9.0 2.0 10.0

PLZ

OEAB to B 2.0 10.5 1.0 12.0 2.0 11.0

tS(H) Setup Time, HIGH or 5.0 5.0 5.0

tS(L) LOW, Bus to Clock 5.0 5.0 5.0 tH(H) Hold Time, HIGH or 2.0 2.5 2.0

tH(L) LOW, Bus to Clock 2.0 2.5 2.0 tW(H) Clock Pulse Width 5.0 5.0 5.0

tW(L) HIGH or LOW 5.0 5.0 5.0

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74F651 • 74F652

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

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74F651 • 74F652 T ransceivers/Registers

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

Package Number N24C

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support de vices o r systems a re devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical com ponent in any com ponent of a life supp ort device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

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