Datasheet 74f647, 74f649 DATASHEETS (Philips)

INTEGRATED CIRCUITS

74F647

Octal transceiver/register, non-inverting (open-collector)

74F649

Octal transceiver/register, inverting (open-collector)

Product specification IC15 Data Handbook

1992 Feb 28

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Philips Semiconductors Product specification

74F647/74F649Octal transceivers/registers (open-collector)

74F647 Octal Transceiver/Register, Non-inverting (Open Collector) 74F649 Octal Transceiver/Register, Inverting (Open Collector)

FEA TURES

•High impedance NPN base inputs for reduced loading

(20µA in High and Low states)

•Independent registers for A and B buses

•Multiplexed real-time and stored data

•Choice of non-inverting and inverting data paths

•Open Collector outputs

•300 mil wide 24-pin Slim Dip package

DESCRIPTION

The 74F647 and 74F649 Transceivers/Registers consist of bus transceiver circuits with open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a High logic level. Output Enable (OE provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or both.

The select (SAB, SBA) controls can multiplex stored and real-time (transparent mode) data. The DIR determines which bus will receive

PIN CONFIGURATION – 74F647

) and DIR pins are

data when the Output Enable, OE mode (Output Enable, OE

is active Low. In the isolation

= High), data from Bus A may be stored in the B register and/or data from Bus B may be stored in the A register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The following examples demonstrate the four fundamental bus-management functions that can be performed with the 74F647 and 74F649.

TYPE

TYPICAL

f

max

TYPICAL SUPPL Y CURRENT

(TOTAL)

74F647 65MHz 125mA 74F649 65MHz 125mA

ORDERING INFORMATION

COMMERCIAL RANGE

DESCRIPTION

24-pin plastic Slim

VCC = 5V ±10%,

T

= 0°C to +70°C

amb

PKG DWG #

N74F647N, N74F649N SOT222-1

DIP (300mil)

24-pin plastic SOL N74F647D, N74F649D SOT137-1

PIN CONFIGURATION – 74F649

CPAB

SAB

DIR

GND

1 2 3 4

A0

5

A1

6

A2

7

A3

8

A4

9

A5

10

A6

11

A7

24 23 22 21 20 19 18 17 16 15 14 1312

SF01196

V

CC

CPBA SBA OE

B0 B1

B2 B3

B4 B5 B6 B7

CPAB

SAB

DIR

GND

1 2 3 4

A0

5

A1

6

A2

7

A3

8

A4

9

A5

10

A6

11

A7

24 23 22 21 20 19 18 17 16 15 14 1312

SF01196

V

CC

CPBA SBA OE

B0 B1

B2 B3

B4 B5 B6 B7

1992 Feb 28 853-0876 05853

2

Philips Semiconductors Product specification

74F647/74F649Octal transceivers/registers (open-collector)

LOGIC SYMBOL – 74F647

4567891011

A0 A1 A2 A3 A4 A5 A6 A7

CPAB

1

SAB

2

DIR

3

CPBA SBA OE

B0 B1 B2 B3 B4 B5 B6 B7

20 19 18 17 16 15 14 13

VCC=Pin 24 GND=Pin 12

23 22 21

LOGIC SYMBOL – 74F647

21

3

23 22

1 2

4

5

6

7

8

9

10

11

G3 3EN1(BA) 3EN2(AB) C4 G5 C6 G7

1

≥

1

6D

1

LOGIC SYMBOL – 74F649

4567891011

A0 A1 A2 A3 A4 A5 A6 A7

CPAB

1

SAB

2

DIR

3

CPBA SBA OE

B0 B1 B2 B3 B4 B5 B6 B7

20 19 18 17 16 15 14 13

SF01198

SF01197

VCC=Pin 24 GND=Pin 12

23 22 21

LOGIC SYMBOL – 74F648

21

3

23 22

1 2

4D

5

1

5

7

≥ 1

2

7

20

19

18

17

16

15

14

13

4

5

6

7

8

9

10

11

G3 3EN1(BA) 3EN2(AB) C4 G5 C6 G7

1

≥

1

6D

1

4D

5

1

5

7

≥ 1

2

7

20

19

18

17

16

15

14

13

SF01199

REAL TIME BUS TRANSFER

BUS B TO BUS A

BUS A BUS B BUS A BUS B BUS A BUS B BUS A BUS B

OE

DIRLCPABXCPBAXSABXSBA

L

1992 Feb 28

REAL TIME BUS TRANSFER

BUS A TO BUS B

OELDIRHCPABXCPBAXSABLSBA

X

OE

DIR X X H

STORAGE FROM

A, B, OR A AND B

CPABXCPBAXSAB X X X

SBA

X

TRANSFER STORED DATA

DIR

OE

L

H

3

TO A OR B

CPAB

X

HorL

SF01200

CPBA H or L

X

SAB

X H

SF01201

SBA

H X

Philips Semiconductors Product specification

74F647/74F649Octal transceivers/registers (open-collector)

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

74F(U.L.)

HIGH/LOW

A0 - A7 A inputs 1.0/0.033 20µA/20µA B0 - B7 B inputs 1.0/0.033 20µA/20µA CPAB A-to-B clock input 1.0/0.033 20µA/20µA CPBA B-to-A clock input 1.0/0.033 20µA/20µA SAB A-to-B select input 1.0/0.033 20µA/20µA SBA B-to-A select input 1.0/0.033 20µA/20µA DIR Data flow Directional control enable input 1.0/0.066 20µA/20µA OE Output Enable input 1.0/0.066 20µA/20µA A0 - A7 A outputs OC/106.7 OC/64mA B0 - B7 B outputs OC/106.7 OC/64mA

NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state. OC = Open Collector

FUNCTION TABLE

INPUTS DATA I/O OPERATING MODE

OE DIR CPAB CPBA SAB SBA A0-A7 B0-B7

X X ↑ X X X Input Unspecified* Store A, B unspecified* Store A, B unspecified* X X X ↑ X X Unspecified* Input Store B, A unspecified* Store B, A unspecified*

H

H L

L L

L

H = High voltage level L = Low voltage level X = Don’t care ↑ = Low-to-High clock transition * = The data output function may be enabled or disabled by various signals at the OE

X

X↑H or L↑H or LXX L

L HHH or L

X XXH or LXX

X

L H

X X

L H

X

Input Input

Output Input

Input Output Real time A data to B bus

X

Store A and B data

Isolation, hold storage

Real time B data to A bus

Stored B data to A bus

Stored A data to B bus

and DIR inputs. Data input functions are always

enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.

LOAD VALUE

HIGH/LOW

Store A and B data

Isolation, hold storage

Real time B data to A bus

Stored B data to A bus

Real time A data to B bus

Stored A data to B bus

LOGIC DIAGRAM – 74F647

21

OE

3

DIR

23

CPBA

22

SBA

1

CPAB

2

SAB

1 of 8 Channels

4

A0

1D

C1

To 7 other channels

1992 Feb 28

LOGIC DIAGRAM – 74F649

21

OE

3

DIR

23

CPBA

22

SBA

1

CPAB

2

SAB

1D

C1

20

SF01202

B0

A0

1 of 8 Channels

4

1D

C1

To 7 other channels

4

1D

C1

20

B0

SF01203

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

1

VOLLow-level output voltage

V

MAX

I

In ut current at

ICCSupply current (total)

V

MAX

74F647/74F649Octal transceivers/registers (open-collector)

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

V V I

IN

V I

OUT

T T

CC IN

OUT

amb stg

Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to +V Current applied to output in Low output state 128 mA Operating free-air temperature range 0 to +70 °C Storage temperature –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

V V V I V I T

CC IH IL

IK

OH

OL

amb

Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V Low-level input voltage 0.8 V Input clamp current –18 mA High-level output voltage 4.5 V Low-level output current 64 mA Operating free-air temperature range 0 70 °C

PARAMETER RATING UNIT

CC

V

LIMITS

MIN NOM MAX

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

LIMITS UNIT

MIN TYP

I

OH

V

I

IH

I

IL

NOTES:

High-level output current

VCC = MIN,

p

VIH = MIN,

Input clamp voltage VCC = MIN, II = I Input current at

maximum input voltage

Others VCC = 0.0, VI = 7.0V 100 µA

An, Bn VCC = 5.5V, VI = 5.5V 1 mA High-level input current VCC = MAX, VI = 2.7V 20 Low-level input current VCC = MAX, VI = 0.5V –20 µA

I

pp

CCH

I

CCL

VCC = MIN, VIL = MAX, VIH = MIN, VOH = MAX

=

IL

IOL = 48mA ±10%V IOL = 64mA ±5%V

IK

=

CC

1. For conditions shown as MIN or Max, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

= 5V, T

CC

amb

= 25°C.

2

MAX

250 µA

0.38 0.55 V

0.42 0.55 V

–0.73 –1.2 V

µA

105 145 mA 145 200 mA

1992 Feb 28

5

Philips Semiconductors Product specification

74F647/74F649Octal transceivers/registers (open-collector)

AC ELECTRICAL CHARACTERISTICS

LIMITS

T

SYMBOL PARAMETER TEST CONDITION

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

Maximum clock frequency Waveform 1 50 65 40 MHz Propagation delay

CPAB to Bn or CPBA or An Propagation delay

An to Bn or Bn to An Propagation delay

SBA to An or SAB to Bn Propagation delay

OE to An or Bn Propagation delay

DIR to An or Bn

Waveform 1

Waveform 2

Waveform 3 Waveform 2

Waveform 3

Waveform 2

Waveform 3 Waveform 2

Waveform 3

= +25°C T

amb

VCC = +5.0V VCC = +5.0V ± 10%

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

7.0

5.5

7.5

4.0

7.5

4.0

9.0

6.5

9.0

7.0

12.0

8.5

10.5

7.0

11.5

7.0

13.0

10.0

13.0

15.0

11.0

13.5

9.5

14.5

9.5

16.0

12.5

16.0

18.0

= 0°C to +70°C

amb

7.0

5.5

7.5

4.0

7.5

4.0

9.0

6.5

9.0

7.0

16.5

12.0

16.0

10.5

17.0

10.5

18.5

13.5

18.5

20.0

UNIT

ns ns

AC SETUP REQUIREMENTS

LIMITS

T

= +25°C T

SYMBOL PARAMETER TEST CONDITION

amb

VCC = +5.0V VCC = +5.0V ± 10%

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

ts(H) ts(L)

tw(H) tw(L)

Setup time, High or Low An to CPBA or Bn to CPAB

Hold time, High or Low An to CPBA or Bn to CPAB

Pulse width, High or Low CPAB or CPBA

Waveform 4

Waveform 1

4.0

4.0 0

0

4.5

6.0

AC WAVEFORMS

For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.

1/f

MAX

CPBA

CPAB

An or Bn

or

V

M

t

PHL

tW(H)

V

M

tW(L)

V

M

V

t

M

PLH

V

M

SF01161

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock Frequency

An or Bn

Bn or An

Waveform 2. Propagation Delay, An to Bn or Bn to An and

SBA to An or SAB to Bn

= 0°C to +70°C

amb

UNIT

5.0

5.0 0

0

4.5

6.5

V

M

t

PHL

V

M

t

PLH

V

M

V

M

ns ns

SBA or SAB

An or Bn

SF00395

1992 Feb 28

6

Philips Semiconductors Product specification

74F647/74F649Octal transceivers/registers (open-collector)

AC WAVEFORMS (Continued)

For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.

t

PHL

V

M

SBA or SAB

SF00396

An or Bn

CPBA

CPAB

V

M

ts(H) ts(L)th(H) th(H)

or

V

M

An or Bn

Bn or An

V

t

PLH

M

V

M

V

M

Waveform 3. Propagation Delay, An to Bn or Bn to An and

SBA to An or SAB to Bn

Waveform 4. Data Setup and Hold Times

TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS

18

16

PROPAGATION

DELAY (ns)

14

12

10

8

6

4

t

PLH

PHL

VMV

M

V

M

SF01165

2

0

0 100 200 300 400 500 600

LOAD RESISTOR ()

NOTE:

When using open-collector part, the value of the pull-up resistor greatly affects the value of the t value from 500 to 100 will improve the t user must take certain that the total I

OL

up to 50% with only slight increase in the t

PLH

. However, if the pull-up resistor is changed, the

PHL

current through the resistor and the total IIL’s of the receivers do not exceed the IOL maximum

specification.

SF01208

. For example, changing the pull-up resistor

PLH

1992 Feb 28

7

Philips Semiconductors Product specification

74F647/74F649Octal transceivers/registers (open-collector)

TEST CIRCUIT AND WAVEFORMS

V

CC

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

Test Circuit for Open Collector Outputs

SWITCH POSITION

TEST SWITCH

Open Collector closed All other open

7.0V

R

L

C

R

L

NEGATIVE PULSE

POSITIVE PULSE

90%

10%

V

M

10%

t

THL (tf

t

TLH (tr

90%

V

M

Input Pulse Definition

t

w

V

M

10%

)

t

)

TLH (tr

t

)

THL (tf

90%

V

M

t

w

90%

10%

AMP (V)

0V

AMP (V)

0V

DEFINITIONS:

= Load resistor;

R

L

see AC electrical characteristics for value.

C

= Load capacitance includes jig and probe capacitance;

L

see AC electrical characteristics for value.

R

= T ermination resistance should be equal to Z

T

pulse generators.

OUT

of

family

74F

INPUT PULSE REQUIREMENTS

V

amplitude

3.0V

M

1.5V

rep. rate

1MHz 500ns

t

w

t

TLHtTHL

2.5ns 2.5ns

SF00195

1992 Feb 28

8

Philips Semiconductors Product specification

Transceivers/registers

DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1

74F647, 74F649

1992 Feb 28

9

Philips Semiconductors Product specification

Transceivers/registers

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

74F647, 74F649

1992 Feb 28

10

Philips Semiconductors Product specification

Transceivers/registers

74F647, 74F649

NOTES

1992 Feb 28

11

Philips Semiconductors Product specification

Transceivers/registers

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

74F647, 74F649

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 10-98 Document order number: 9397-750-05152

 

yyyy mmm dd

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