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© 1999 Fairchild Semiconductor Corporation DS009580 www.fairchildsemi.com
March 1988
Revised August 1999
74F646 • 74F646B • 74F648 Octal Transceiver/ Register with 3-STATE Outputs
74F646 • 74F646B • 74F648
Octal Transceiver/Register with 3-STATE Outputs
General Description
These devices consist of bus transceive r circuits with 3STATE , D-type flip-fl ops, and c ontrol circui try arranged f or
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control G
and direction pins are pr ovided to control the tr ansceiver function. In the tran sceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control G
is Active LOW.
In the isolation mode (con trol G
HIGH), A data may be
stored in the B register and /or B d ata ma y be store d in the
A register.
Features
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data
■ 74F648 has inverting data paths
■ 74F646/74F646B have non-inverting data paths
■ 74F646B is a faster version of the 74F646
■ 3-STATE outputs
■ 300 mil slim DIP
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Order Number Package Number Package Description
74F646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F646MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F646BSC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F646BSPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F648SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F648SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
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74F646 • 74F646B • 74F648
Logic Symbols
74F646/74F646B
IEEE/IEC
74F646/74F646B
74F648
IEEE/IEC
74F648
Connection Diagrams
74F646/74F646B 74F648
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74F646 • 74F646B • 74F648
Unit Loading/Fan Out
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Irrelevant
= LOW-to - HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G
and DIR Inputs. Data input functions are always enabled; i.e ., d at a
at the bus pins will be stored on every LOW-to-HIGH transition of the clo c k in puts.
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
A0–A
7
Data Register A Inputs/ 3.5/1.083 70 µA/−650 µA
3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (48 mA)
B
0–B7
Data Register B Inputs/ 3.5/1.083 70 µA/−650 µA
3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (48 mA)
CPAB, CPBA Clock Pulse Inputs 1.0/1.0 20 µA/−0.6 mA
SAB, SBA Select Inputs 1.0/1.0 20 µA/−0.6 mA
G
Output Enable Input 1.0/1.0 20 µA/−0.6 mA
DIR Direction Control Input 1.0/1.0 20 µA/−0.6 mA
Inputs Data I/O (Note 1)
Function
G
DIR CPAB CPBA SAB SBA
A
0–A7B0–B7
H X H or L H or L X X Isolation
HX
X X X Input Input Clock An Data into A Register
HXX
X X Clock Bn Data into B Register
LHXXLX A
n
to Bn—Real Time (Transparent Mode)
LH
X L X Input Output Clock An Data into A Register
L H H or L X H X A Register to B
n
(Stored Mode)
LH
X H X Clock An Data into A Register and Output to B
n
LLXXXL Bn to An—Real Time (Transparent Mode)
LLX
X L Output Input Clock Bn Data into B Register
L L X H or L X H B Register to A
n
(Stored Mode)
LLX
X H Clock Bn Data into B Register and Output to A
n
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74F646 • 74F646B • 74F648
Logic Diagrams
74F646/74F646B
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
74F648
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
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74F646 • 74F646B • 74F648
Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 3: Either voltage limit or curren t limit is sufficient to protect in puts.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 3) −0.5V to +7.0V
Input Current (Note 3) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambi ent Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins)
V
OH
Output HIGH
10% V
CC
2.0 V Min IOH = −15 mA (An, Bn)
Voltage
V
OL
Output LOW
10% V
CC
0.55 V Min IOL = 64 mA (An, Bn)
Voltage
I
IH
Input HIGH
5.0 µAMaxVIN = 2.7V (Non I/O Pins)
Current
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V (Non I/O Pins)
Breakdown Test
I
BVIT
Input HIGH Current
0.5 mA Max VIN = 5.5V (An, Bn)
Breakdown (I/O)
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6 mA Max VIN = 0.5V (Non I/O Pins)
IIH + I
OZH
Output Leakage Current 70 µAMaxV
OUT
= 2.7V (An, Bn)
IIL + I
OZL
Output Leakage Current −650 µAMaxV
OUT
= 0.5V (An, Bn)
I
OS
Output Short-Circuit Current −100 −225 mA Max V
OUT
= 0V
I
ZZ
Bus Drainage Test 500 µA0.0VV
OUT
= 5.25V
I
CCH
Power Supply Current 135 mA Max VO = HIGH
I
CCL
Power Supply Current 150 mA Max VO = LOW
I
CCZ
Power Supply Current 150 mA Max VO = HIGH Z
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74F646 • 74F646B • 74F648
AC Electrical Characteristics 74F646/74F648
AC Operating Requirements 74F646/74F648
Symbol Parameter
TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF CL = 50 pF
Min Max Min Max Min Max
f
MAX
Maximum Clock Frequency 90 75 90 MHz
t
PLH
Propagation Delay 2.0 7.0 2.0 8.5 2.0 8.0
ns
t
PHL
Clock to Bus 2.0 8.0 2.0 9.5 2.0 9.0
t
PLH
Propagation Delay 1.0 7.0 1.0 8.0 1.0 7.5
ns
t
PHL
Bus to Bus (74F646) 1.0 6.5 1.0 8.0 1.0 7.0
t
PLH
Propagation Delay 2.0 8.5 1.0 10.0 2.0 9.0
ns
t
PHL
Bus to Bus (74F648) 1.0 7.5 1.0 9.0 1.0 8.0
t
PLH
Propagation Delay 2.0 8.5 2.0 11.0 2.0 9.5
ns
t
PHL
SBA or SAB to A or B 2.0 8.0 2.0 10.0 2.0 9.0
t
PZH
Enable Time 2.0 8.5 2.0 10.0 2.0 9.0
ns
t
PZL
OE to A or B
2.0 12.0 2.0 13.5 2.0 12.5
t
PHZ
Disable Time 1.0 7.5 1.0 9.0 1.0 8.5
ns
t
PLZ
OE to A or B
2.0 9.0 2.0 11.0 2.0 9.5
t
PZH
Enable Time 2.0 14.0 2.0 16.0 2.0 15.0
ns
t
PZL
DIR to A or B 2.0 13.0 2.0 15.0 2.0 14.0
t
PHZ
Disable Time 1.0 9.0 1.0 10.0 1.0 9.5
ns
t
PLZ
DIR to A or B 2.0 11.0 2.0 12.0 2.0 11.5
Symbol Parameter
TA = +25°CT
A
= −55°C to +125°CTA = 0°C to +70°C
UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V
Min Max Min Max Min Max
tS(H) Setup Time, HIGH or LOW 5.0 5.0 5.0
ns
tS(L) Bus to Clock 5.0 5.0 5.0
tH(H) Hold Time, HIGH or LOW 2.0 2.5 2.0
ns
tH(L) Bus to Clock 2.0 2.5 2.0
tW(H) Clock Pulse Width 5.0 5.0 5.0
ns
tW(L) HIGH or LOW 5.0 5.0 5.0
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74F646 • 74F646B • 74F648
AC Electrical Characteristics 74F646B
AC Operating Requirements 74F646B
Symbol Parameter
TA = +25°CT
A
= −55°C to +125°CTA = 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF CL = 50 pF
Min Max Min Max Min Max
f
MAX
Maximum Clock Frequency 165 150 MHz
t
PLH
Propagation Delay 2.5 7.0 2.5 8.0
ns
t
PHL
Clock to Bus 3.0 7.5 3.0 8.0
t
PLH
Propagation Delay 2.0 6.0 2.0 7.0
ns
t
PHL
Bus to Bus 2.0 6.0 2.0 7.0
t
PLH
Propagation Delay 2.5 7.5 2.5 8.5
ns
t
PHL
SBA or SAB to A or B 2.5 7.5 2.5 8.5
t
PZH
Enable Time 2.5 6.5 2.5 8.0
ns
t
PZL
OE to A or B
2.5 9.0 2.5 10.0
t
PHZ
Disable Time 1.5 6.5 1.5 7.5
ns
t
PLZ
OE to A or B
2.07.0 2.08.5
t
PZH
Enable Time 2.0 7.0 2.0 8.5
ns
t
PZL
DIR to A or B 3.0 9.5 3.0 10.0
t
PHZ
Disable Time 1.5 7.5 1.5 8.5
ns
t
PLZ
DIR to A or B 2.5 8.5 2.5 9.5
Symbol Parameter
TA = +25°CT
A
= −55°C to +125°CTA = 0°C to +70°C
UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V
Min Max Min Max Min Max
tS(H) Setup Time, HIGH or LOW 5.0 4.0
ns
tS(L) Bus to Clock 5.0 4.0
tH(H) Hold Time, HIGH or LOW 1.5 1.5
ns
tH(L) Bus to Clock 1.5 1.5
tW(H) Clock Pulse Width 5.0 5.0
ns
tW(L) HIGH or LOW 5.0 5.0
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74F646 • 74F646B • 74F648
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24
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74F646 • 74F646B • 74F648 Octal Tr ansceiver/Register with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the
user.
2. A critical com ponen t in any compo nent o f a l ife supp ort
device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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