Datasheet 74F648SPC, 74F648SCX, 74F648SC, 74F646BSPC, 74F646BSCX Datasheet (Fairchild Semiconductor)

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March 1988 Revised August 1999

74F646 • 74F646B • 74F648 Octal Transceiver/Register with 3-STATE Outputs

74F646 • 74F646B • 74F648 Octal Transceiver/ R egister with 3-STATE Outputs

General Description

These devices consist of bus transceive r circuits with 3STATE , D-type flip-fl ops, and c ontrol circui try arranged f or multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control G vided to control the tr ansceiver function. In the tran sceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control G In the isolation mode (control G stored in the B register and/or B d ata ma y be store d in the A register.

and direction pins are pr o-

is Active LOW.

HIGH), A data may be

Features

■ Independent registers for A and B buses

■ Multiplexed real-time and stored data

■ 74F648 has inverting data paths

■ 74F646/74F646B have non-inverting data paths

■ 74F646B is a faster version of the 74F646

■ 3-STATE outputs

■ 300 mil slim DIP

Ordering Code:

Order Number Package Number Package Description

74F646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F646MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74F646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 74F646BSC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F646BSPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 74F648SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F648SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.

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Logic Symbols

74F646 • 74F646B • 74F648

74F646/74F646B

IEEE/IEC

74F646/74F646B

74F648

IEEE/IEC

74F648

Connection Diagrams

74F646/74F646B 74F648

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Unit Loading/Fan Out

Pin Names Description

A0–A

Data Register A Inputs/ 3.5/1.083 70 µA/−650 µA 3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (4 8 mA)

0–B7

Data Register B Inputs/ 3.5/1.083 70 µA/−650 µA

3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (4 8 mA) CPAB, CPBA Clock Pulse Inputs 1.0/1.0 20 µA/−0.6 mA SAB, SBA Select Inputs 1.0/1.0 20 µA/−0.6 mA G

Output Enable Input 1.0/1.0 20 µA/−0.6 mA DIR Direction Control Input 1.0/1.0 20 µA/−0.6 mA

U.L.

HIGH/LOW

Output I

Function Table

Input I

74F646 • 74F646B • 74F648

IH/IIL OH/IOL

Inputs Data I/O (Note 1)

DIR CPAB CPBA SAB SBA

0–A7B0–B7

Function

H X H or L H or L X X Isolation



HX HXX

LHXXLX A

LH L H H or L X H X A Register to B LH

X X X Input Input Clock An Data into A Register



X X Clock Bn Data into B Register

to Bn—Real Time (Transparent Mode)



X L X Input Output Clock An Data into A Register



X H X Clock An Data into A Register and Output to B

(Stored Mode)

LLXXXL Bn to An—Real Time (Transparent Mode)



LLX L L X H or L X H B Register to A LLX

H = HIGH Voltage Level

L = LOW Voltage Level X = Irrelevant



= LOW-to - HIGH Transition

Note 1: The data output functions may be enabled or disabled by various signals at the G at the bus pins will be stored on every LOW-to-HIGH transition of the clo c k in puts.

X L Output Input Clock Bn Data into B Register

(Stored Mode)



X H Clock Bn Data into B Register and Output to A

and DIR Inputs. Data input functions are always enabled; i.e ., d at a

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Logic Diagrams

74F646/74F646B

74F646 • 74F646B • 74F648

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and shou ld not be used to estimate propagation delays.

74F648

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and shou ld not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 2) Recommended Operating

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C

Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V) Standard Output −0.5V to V 3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

ESD Last Pa ssing Voltage (Min) 4000V

Conditions

Free Air Ambient Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Note 2: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 3: Either voltage limit or curren t limit is sufficient to protect in puts.

(mA)

DC Electrical Characteristics

74F646 • 74F646B • 74F648

Symbol Parameter Min Typ Max Units

BVI

BVIT

CEX

IIH + I IIL + I I

CCH

CCL

CCZ

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal Input LOW Voltage 0.8 V Recognized as a LOW Signal Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins) Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test All Other Pins Grounded Output Leakage Circuit Current All Other Pins Grounded

10% V

2.0 V Min IOH = −15 mA (An, Bn)

0.55 V Min IOL = 64 mA (An, Bn)

5.0 µAMaxVIN = 2.7V (Non I/O Pins)

7.0 µAMaxVIN = 7.0V (Non I/O Pins)

0.5 mA Max VIN = 5.5V (An, Bn)

50 µAMaxV

4.75 V 0.0

3.75 µA0.0

Input LOW Current −0.6 mA Max VIN = 0.5V (Non I/O Pins) Output Leakage Current 70 µAMaxV

OZH

Output Leakage Current −650 µAMaxV

OZL

Output Short-Circuit Current −100 −225 mA Max V Bus Drainage Test 500 µA0.0VV Power Supply Current 135 mA Max VO = HIGH Power Supply Current 150 mA Max VO = LOW Power Supply Current 150 mA Max VO = HIGH Z

OUT

Conditions

= V

IID = 1.9 µA

= 150 mV

IOD

= 2.7V (An, Bn)

OUT

= 0.5V (An, Bn)

OUT

= 0V

OUT

= 5.25V

OUT

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AC Electrical Characteristics 74F646/74F648

TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C

Symbol Parameter

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Max Min Max Min Max

MAX

PLH

PHL

PLH

PHL

PLH

PHL

74F646 • 74F646B • 74F648

PLH

PHL

PZH

PZL

PHZ

PLZ

PZH

PZL

PHZ

PLZ

Maximum Clock Frequency 90 75 90 MHz Propagation Delay 2.0 7.0 2.0 8.5 2.0 8.0 Clock to Bus 2.0 8.0 2.0 9.5 2.0 9.0 Propagation Delay 1.0 7.0 1.0 8.0 1.0 7.5 Bus to Bus (74F646) 1.0 6.5 1.0 8.0 1.0 7.0 Propagation Delay 2.0 8.5 1.0 10.0 2.0 9.0 Bus to Bus (74F648) 1.0 7.5 1.0 9.0 1.0 8.0 Propagation Delay 2.0 8.5 2.0 11.0 2.0 9.5 SBA or SAB to A or B 2.0 8.0 2.0 10.0 2.0 9.0 Enable Time 2.0 8.5 2.0 10.0 2.0 9.0 OE to A or B

2.0 12.0 2.0 13.5 2.0 12.5 Disable Time 1.0 7.5 1.0 9.0 1.0 8.5 OE to A or B

2.0 9.0 2.0 11.0 2.0 9.5 Enable Time 2.0 14.0 2.0 16.0 2.0 15.0

DIR to A or B 2.0 13.0 2.0 15.0 2.0 14.0 Disable Time 1.0 9.0 1.0 10.0 1.0 9.5 DIR to A or B 2.0 11.0 2.0 12.0 2.0 11.5

AC Operating Requirements 74F646/74F648

TA = +25°CT

Symbol Parameter

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 5.0 5.0 5.0 tS(L) Bus to Clock 5.0 5.0 5.0 tH(H) Hold Time, HIGH or LOW 2.0 2.5 2.0 tH(L) Bus to Clock 2.0 2.5 2.0 tW(H) Clock Pulse Width 5.0 5.0 5.0 tW(L) HIGH or LOW 5.0 5.0 5.0

= −55°C to +125°CTA = 0°C to +70°C

Units

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

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AC Electrical Characteristics 74F646B

74F646 • 74F646B • 74F648

Symbol Parameter

TA = +25°CT

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

= −55°C to +125°CTA = 0°C to +70°C

Min Max Min Max Min Max

f t t t t t t t t

t t

t t t t

MAX PLH PHL PLH PHL PLH PHL PZH PZL

PHZ PLZ

PZH PZL PHZ PLZ

Maximum Clock Frequency 165 150 MHz Propagation Delay 2.5 7.0 2.5 8.0 Clock to Bus 3.0 7.5 3.0 8.0 Propagation Delay 2.0 6.0 2.0 7.0 Bus to Bus 2.0 6.0 2.0 7.0 Propagation Delay 2.5 7.5 2.5 8.5 SBA or SAB to A or B 2.5 7.5 2.5 8.5 Enable Time 2.5 6.5 2.5 8.0 OE to A or B

2.5 9.0 2.5 10.0 Disable Time 1.5 6.5 1.5 7.5 OE to A or B

2.07.0 2.08.5 Enable Time 2.0 7.0 2.0 8.5

DIR to A or B 3.0 9.5 3.0 10.0 Disable Time 1.5 7.5 1.5 8.5 DIR to A or B 2.5 8.5 2.5 9.5

AC Operating Requirements 74F646B

TA = +25°CT

Symbol Parameter

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 5.0 4.0 tS(L) Bus to Clock 5.0 4.0 tH(H) Hold Time, HIGH or LOW 1.5 1.5 tH(L) Bus to Clock 1.5 1.5 tW(H) Clock Pulse Width 5.0 5.0 tW(L) HIGH or LOW 5.0 5.0

= −55°C to +125°CTA = 0°C to +70°C

Units

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

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Physical Dimensions inches (millimeters) unless otherwise noted

74F646 • 74F646B • 74F648

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package Number M24B

Package Number MSA24

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74F646 • 74F646B • 74F648 Octal Transceiver/Register with 3-STATE Outputs

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent license s are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices o r syst ems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the user.

Package Number N24C

2. A critical com ponen t in any com ponen t of a life supp ort device or system whose failu re to perform can b e reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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