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74F640 • 74F645
Octal Bus Transceiver with 3-STATE Outputs
74F640 • 74F645 Octal Bus Transceiver with 3-STATE Outputs
July 1989
Revised August 1999
General Description
These devices are octal bus transceivers designed for
asynchronous two-way data flow between the A and B busses. Both busses are capa ble of sinking 64 mA, have 3STATE outputs, and a common output enable pin. The
direction of data flow is d eterm ined by t he t ransmit/ receive
) input. The 74F645 is a high speed/low power version
(T/R
of the 74F245. The 74F 640 is an inverting option of the
74F645.
Features
■ Designed for asynchronous two- way data flow between
busses
■ Outputs sink 64 mA
■ Transmit/receive (T/R
data flow
■ 74F645 is a lower power, faster version of the 74F245
■ 74F640 is an inverting option of the 74F645
) input controls the direction of
Ordering Code:
Order Number Package Number Package Description
74F640SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F640PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F645PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Logic Symbol Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS010267 www.fairchildsemi.com
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Unit Loading/Fan Out
Pin Names Description
Output Enable Input (Active LOW)
Transmit/Receive Input 1.0/1.0 20 µA/−0.6 mA
Side A Inputs or 3.5/0.667 70 µA/−0.4 mA
3-STATE Outputs 600/106.6 −12 mA/64 mA
Side B Inputs or 3.5/0.667 70 µA/−0.4 mA
3-STATE Outputs 600/106.6 −12 mA/64 mA
74F640 • 74F645
OE
T/R
A
B
0–A7
0–B7
Functional Description
The output enable (OE) is active LOW. If the device is disabled (OE
state. The transmit/receive input (T/R
data is transmitted from the A bus to the B bus o r from th e
B bus to the A bus. When T/R
A bus. If T/R
HIGH), the outpu ts are in the high impedance
) controls whether
is LOW, B data is sent to the
is HIGH, A data is sent to the B bus.
Logic Diagram
Function Table
Inputs Outputs
T/R 74F640 74F645
OE
L L Bus B
L H Bus A
HX Z Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance State
74F640
U.L.
HIGH/LOW
1.0/1.0 20 µA/−0.6 mA
data to Bus A Bus B data to Bus A
data to Bus B Bus A data to Bus B
Input I
Output I
IH/IIL
OH/IOL
74F645
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Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
Pin Potential to Ground Pin −0.5V to +7.0V
V
CC
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
ESD Last Passing Voltage (Min) 4000V
Conditions
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyon d which the device
CC
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
(mA)
DC Electrical Characteristics
74F640 • 74F645
Symbol Parameter Min Typ Max Units
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
BVIT
I
CEX
V
ID
I
OD
I
IL
IIH + I
IIL + I
I
OS
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins)
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown (I/O)
Output HIGH
Leakage Current
Input Leakage
Test All Other Pins Grounded
Output Leakage
Circuit Current All Other Pins Grounded
10% V
10% V
2.0 V Min IOH = −15 mA (An, Bn)
CC
CC
0.55 V Min IOL = 64 mA (An, Bn)
5.0 µAMaxVIN = 2.7V (Non I/O Pins)
7.0 µAMaxVIN = 7.0V (Non I/O Pins)
0.5 mA Max VIN = 5.5V (An, Bn)
50 µAMaxV
4.75 V 0.0
3.75 µA0.0
Input LOW Current −0.6 mA Max VIN = 0.5V (Non I/O Pins)
Output Leakage Current 70 µAMaxV
OZH
Output Leakage Current −650 µAMaxV
OZL
Output Short-Circuit Current −100 −225 mA Max V
Bus Drainage Test 500 µA0.0VV
Power Supply Current (74F640) 80 mA Max VO = HIGH, VIN = 0.2V
Power Supply Current (74F640) 80 mA Max VO = LOW
Power Supply Current (74F640) 96 mA Max VO = HIGH Z
Power Supply Current (74F645) 65 mA Max VO = HIGH
Power Supply Current (74F645) 80 mA Max VO = LOW, VIN = 0.2V
Power Supply Current (74F645) 90 mA Max VO = HIGH Z
V
CC
OUT
Conditions
= V
CC
IID = 1.9 µA
V
= 150 mV
IOD
= 2.7V (An, Bn)
OUT
= 0.5V (An, Bn)
OUT
= 0V
OUT
= 5.25
OUT
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AC Electrical Characteristics 74F640
Symbol Parameter
t
PLH
t
PHL
74F640 • 74F645
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay 2.5 7.5 2.0 8.0
A Input to B Output 2.0 7.0 2.0 7.0
Propagation Delay 2.5 7.5 2.0 8.0
B Input to A Output 2.0 7.0 2.0 7.0
Enable Time 2.5 7.5 2.0 9.0 ns
OE Input to A Output
Disable Time 1.5 7.0 1.0 7.5
OE Input to A Output
Enable Time 2.5 7.5 2.0 9.0 ns
OE Input to B Output
Disable Time 1.5 7.0 1.0 7.5
OE Input to B Output
AC Electrical Characteristics 74F645
Symbol Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay 1.5 6.0 1.5 7.0
A Input to B Output 2.0 7.0 2.0 7.5
Propagation Delay 1.5 6.0 1.5 7.0
B Input to A Output 2.0 7.0 2.0 7.5
Enable Time 2.5 8.0 2.0 9.0 ns
OE Input to A Output
Disable Time 1.5 7.0 1.0 8.0
OE Input to A Output
Enable Time 2.5 7.5 2.0 9.5 ns
OE Input to B Output
Disable Time 1.5 6.5 1.0 7.5
OE Input to B Output
TA = +25°CT
= 0°C to +70°C
A
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
2.5 8.0 2.0 8.5
1.5 6.0 1.5 6.0
2.5 8.0 2.0 8.5
1.5 6.0 1.5 6.0
TA = +25°CT
= 0°C to +70°C
A
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
2.5 8.5 2.0 8.5
1.0 5.5 1.0 5.5
2.5 8.5 2.5 9.0
1.0 5.5 1.0 5.5
Units
ns
ns
Units
ns
ns
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Physical Dimensions inches (millimeters) unless otherwise noted
74F640 • 74F645
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
74F640 • 74F645 Octal Bus Tran sceiver with 3-STATE Outputs
Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
2. A critical component in any compon ent of a lif e supp ort
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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