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© 1999 Fairchild Semiconductor Corporation DS010267 www.fairchildsemi.com
July 1989
Revised August 1999
74F640 • 74F645 Octal Bus Transceiver with 3-STATE Outputs
74F640 • 74F645
Octal Bus Transceiver with 3-STATE Outputs
General Description
These devices are octal bus transceivers designed for
asynchronous two-way data flow between the A and B busses. Both busses are capa ble of sinking 64 mA, have 3STATE outputs, and a common output enable pin. The
direction of data flow is d eterm ined by t he tran smit/ receive
(T/R
) input. The 74F645 is a high speed/low power version
of the 74F245. The 74F 640 is an inverting option of the
74F645.
Features
■ Designed for asynchronous two- way data flow between
busses
■ Outputs sink 64 mA
■ Transmit/receive (T/R
) input controls the direction of
data flow
■ 74F645 is a lower power, faster version of the 74F245
■ 74F640 is an inverting option of the 74F645
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbol Connection Diagram
Order Number Package Number Package Description
74F640SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F640PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F645PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F640 • 74F645
Unit Loading/Fan Out
Functional Description
The output enable (OE) is active LOW. If the device is disabled (OE
HIGH), the outpu ts are in the high impedance
state. The transmit/receive input (T/R
) controls whether
data is transmitted from the A bu s to the B bus o r from th e
B bus to the A bus. When T/R
is LOW, B data is sent to the
A bus. If T/R
is HIGH, A data is sent to the B bus.
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance State
Logic Diagram
74F640
74F645
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
OE
Output Enable Input (Active LOW)
1.0/1.0 20 µA/−0.6 mA
T/R
Transmit/Receive Input 1.0/1.0 20 µA/−0.6 mA
A
0–A7
Side A Inputs or 3.5/0.667 70 µA/−0.4 mA
3-STATE Outputs 600/106.6 −12 mA/64 mA
B
0–B7
Side B Inputs or 3.5/0.667 70 µA/−0.4 mA
3-STATE Outputs 600/106.6 −12 mA/64 mA
Inputs Outputs
OE
T/R 74F640 74F645
L L Bus B
data to Bus A Bus B data to Bus A
L H Bus A
data to Bus B Bus A data to Bus B
HX Z Z
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74F640 • 74F645
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the r ated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambi ent Temperat ure 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins)
V
OH
Output HIGH
10% V
CC
2.0 V Min IOH = −15 mA (An, Bn)
Voltage
V
OL
Output LOW
10% V
CC
0.55 V Min IOL = 64 mA (An, Bn)
Voltage
I
IH
Input HIGH
5.0 µAMaxVIN = 2.7V (Non I/O Pins)
Current
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V (Non I/O Pins)
Breakdown Test
I
BVIT
Input HIGH Current
0.5 mA Max VIN = 5.5V (An, Bn)
Breakdown (I/O)
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6 mA Max VIN = 0.5V (Non I/O Pins)
IIH + I
OZH
Output Leakage Current 70 µAMaxV
OUT
= 2.7V (An, Bn)
IIL + I
OZL
Output Leakage Current −650 µAMaxV
OUT
= 0.5V (An, Bn)
I
OS
Output Short-Circuit Current −100 −225 mA Max V
OUT
= 0V
I
ZZ
Bus Drainage Test 500 µA0.0VV
OUT
= 5.25
I
CCH
Power Supply Current (74F640) 80 mA Max VO = HIGH, VIN = 0.2V
I
CCL
Power Supply Current (74F640) 80 mA Max VO = LOW
I
CCZ
Power Supply Current (74F640) 96 mA Max VO = HIGH Z
I
CCH
Power Supply Current (74F645) 65 mA Max VO = HIGH
I
CCL
Power Supply Current (74F645) 80 mA Max VO = LOW, VIN = 0.2V
I
CCZ
Power Supply Current (74F645) 90 mA Max VO = HIGH Z
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74F640 • 74F645
AC Electrical Characteristics 74F640
AC Electrical Characteristics 74F645
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
t
PLH
Propagation Delay 2.5 7.5 2.0 8.0
ns
t
PHL
A Input to B Output 2.0 7.0 2.0 7.0
t
PLH
Propagation Delay 2.5 7.5 2.0 8.0
ns
t
PHL
B Input to A Output 2.0 7.0 2.0 7.0
t
PZH
Enable Time 2.5 7.5 2.0 9.0 ns
t
PZL
OE Input to A Output
2.5 8.0 2.0 8.5
t
PHZ
Disable Time 1.5 7.0 1.0 7.5
t
PLZ
OE Input to A Output
1.5 6.0 1.5 6.0
t
PZH
Enable Time 2.5 7.5 2.0 9.0 ns
t
PZL
OE Input to B Output
2.5 8.0 2.0 8.5
t
PHZ
Disable Time 1.5 7.0 1.0 7.5
t
PLZ
OE Input to B Output
1.5 6.0 1.5 6.0
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
t
PLH
Propagation Delay 1.5 6.0 1.5 7.0
ns
t
PHL
A Input to B Output 2.0 7.0 2.0 7.5
t
PLH
Propagation Delay 1.5 6.0 1.5 7.0
ns
t
PHL
B Input to A Output 2.0 7.0 2.0 7.5
t
PZH
Enable Time 2.5 8.0 2.0 9.0 ns
t
PZL
OE Input to A Output
2.5 8.5 2.0 8.5
t
PHZ
Disable Time 1.5 7.0 1.0 8.0
t
PLZ
OE Input to A Output
1.0 5.5 1.0 5.5
t
PZH
Enable Time 2.5 7.5 2.0 9.5 ns
t
PZL
OE Input to B Output
2.5 8.5 2.5 9.0
t
PHZ
Disable Time 1.5 6.5 1.0 7.5
t
PLZ
OE Input to B Output
1.0 5.5 1.0 5.5
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74F640 • 74F645
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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74F640 • 74F645 Octal Bus Tran sceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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