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© 1999 Fairchild Semiconductor Corporation DS009577 www.fairchildsemi.com
April 1988
Revised August 1999
74F620 • 74F623 Inverting Octal Bus Transceiver with 3-STATE Outputs
74F620 • 74F623
Inverting Octal Bus Transceiver with 3-STATE Outputs
General Description
These devices are octal bus transceivers designed for
asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA and have 3STAT E outputs. Dual enable pins (GA B, G
BA) allow data
transmission from the A bus to the B bus or from the B bus
to the A bus. The 74F620 is an inverting option of the
74F623.
Features
■ Designed for asynchronous two- way data flow between
busses
■ Outputs sink 64 mA
■ Dual enable inputs control direction of data flow
■ Guarante ed 4000V minimum ESD protection
■ 74F620 is an inverting option of the 74F623
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbol Connection Diagram
FAST is a regist ered trademark of Fairc hild Semiconductor C orporation
Order Number Package Number Package Description
74F620PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F623SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F623PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F620 • 74F623
Unit Loading/Fan Out
Functional Description
The enable inputs GAB and GBA control whether data is
transmitted from the A bus to the B bus or from the B bus to
the A bus. If both G
BA and GAB are disable d (GBA HIGH
and GAB LOW), the outputs are in the high impedance
state and data is stored at the A and B busses. When G
BA
is active LOW, B data is sent to the A bus. When GA B is
active HIGH, data from the A bu s is sent to the B bus. If
both enable inputs are active (G
BA LOW and GAB HIGH)
B data is sent to the A bus while A data is sent to the B bus.
Function Table
H = HIGH Voltage Level
L = LOW Voltage L ev el
Z = High Impedance
Logic Diagrams
74F620
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
74F623
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
GBA, GAB Enable Inputs 1.0/1.0 20 µA/−0.6 mA
A
0–A7
A Inputs or 3.5/1.083 70 µA/−0.4 mA
3-STATE Outputs 150/40 −3 mA/64 mA
B
0–B7
B Inputs or 3.5/1.083 70 µA/−0.4 mA
3-STATE Outputs 150/40 −3 mA/64 mA
Enable Inputs Operation
G
BA GAB 74F620 74F623
LLB
Data to A Bus B Data to A Bus
HHA
Data to B Bus A Data to B Bus
HL Z Z
LHB
Data to A Bus, B Data to A Bus,
A
Data to B Bus A Data to B Bus
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74F620 • 74F623
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambi ent Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins)
V
OH
Output HIGH
10% V
CC
2.0 V Min IOH = −15 mA (An, Bn)
Voltage
V
OL
Output LOW
10% V
CC
0.55 V Min IOL = 64 mA (An, Bn)
Voltage
I
IH
Input HIGH
5.0 µAMaxVIN = 2.7V
Current
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V (GBA, GAB)
Breakdown Test
I
BVIT
Input HIGH Current
0.5 mA Max VIN = 5.5V (An, Bn)
Breakdown (I/O)
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6 mA Max VIN = 0.5V (Non I/O Pins)
IIH + I
OZH
Output Leakage Current 70 µAMaxV
OUT
= 2.7V (An, Bn)
IIL + I
OZL
Output Leakage Current −650 µAMaxV
OUT
= 0.5V (An, Bn)
I
OS
Output Short-Circuit Current −100 −225 mA Max V
OUT
= 0V
I
ZZ
Bus Drainage Test 500 µA0.0VV
OUT
= 5.25V
I
CCH
Power Supply Current (74F620) 82 mA Max VO = HIGH, VIN = 0.2V
I
CCL
Power Supply Current (74F620) 82 mA Max VO = LOW
I
CCZ
Power Supply Current (74F620) 95 mA Max VO = HIGH Z
I
CCH
Power Supply Current (74F623) 65 mA Max VO = HIGH
I
CCL
Power Supply Current (74F623) 82 mA Max VO = LOW, VIN = 0.2V
I
CCZ
Power Supply Current (74F623) 85 mA Max VO = HIGH Z
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74F620 • 74F623
AC Electrical Characteristics
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
t
PLH
Propagation Delay 2.5 7.5 2.0 8.0
ns
t
PHL
A Input to B Output (74F620) 2.0 7.0 2.0 7.0
t
PLH
Propagation Delay 2.5 7.5 2.0 8.0
ns
t
PHL
B Input to A Output (74F620) 2.0 7.0 2.0 7.0
t
PLH
Propagation Delay 1.5 6.5 1.5 7.5
ns
t
PHL
A Input to B Output (74F623) 2.0 7.0 2.0 7.5
t
PLH
Propagation Delay 1.5 6.5 1.5 7.5
ns
t
PHL
B Input to A Output (74F623) 2.0 7.0 2.0 7.5
t
PZH
Enable Time 2.0 7.0 2.0 8.0
ns
t
PZL
GBA Input to A Output 2.5 8.0 2.0 8.5
t
PHZ
Disable Time 1.5 6.5 1.5 7.5
t
PLZ
GBA Input to A Output 1.0 5.5 1.0 5.5
t
PZH
Enable Time 2.0 7.5 2.0 8.5
ns
t
PZL
GAB Input to B Output (74F620) 3.0 8.0 2.0 8.5
t
PHZ
Disable Time 2.5 8.0 2.0 9.0
t
PLZ
GAB Input to B Output (74F620) 2.0 7.5 2.0 8.0
t
PZH
Enable Time 2.0 7.5 2.0 8.5
ns
t
PZL
GAB Input to B Output (74F623) 2.5 8.0 2.0 8.5
t
PHZ
Disable Time 2.0 8.0 2.0 9.0
t
PLZ
GAB Input to B Output (74F623) 2.0 8.0 2.0 8.0
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74F620 • 74F623
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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74F620 • 74F623 Inverting Octal Bus Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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