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April 1988
Revised August 1999
74F620 • 74F623
Inverting Octal Bus Transceiver with 3-STATE Outputs
74F620 • 74F623 Inverting Octal Bus Tr ansceiver with 3-STATE Outputs
General Description
These devices are octal bus transceivers designed for
asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA and have 3STAT E outputs. Dual enable pins (G AB, G
transmission from the A bus to the B bus or from the B bus
to the A bus. The 74F620 is an inverting option of the
74F623.
BA) allow data
Features
■ Designed for asynchronous two- way data flow between
busses
■ Outputs sink 64 mA
■ Dual enable inputs control direction of data flow
■ Guaranteed 4000V minimum ESD prote ction
■ 74F620 is an inverting option of the 74F623
Ordering Code:
Order Number Package Number Package Description
74F620PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F623SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F623PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Logic Symbol Connection Diagram
FAST is a regist ered trademark of Fair c hild Semiconductor Corporation
© 1999 Fairchild Semiconductor Corporation DS009577 www.fairchildsemi.com
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Unit Loading/Fan Out
74F620 • 74F623
Pin Names Description
GBA, GAB Enable Inputs 1.0/1.0 20 µA/−0.6 mA
A
B
0–A7
0–B7
A Inputs or 3.5/1.083 70 µA/−0.4 mA
3-STATE Outputs 150/40 −3 mA/64 mA
B Inputs or 3.5/1.083 70 µA/−0.4 mA
3-STATE Outputs 150/40 −3 mA/64 mA
U.L.
HIGH/LOW
Input I
Output I
IH/IIL
OH/IOL
Functional Description
The enable inputs GA B and GBA control whether data is
transmitted from the A bus to the B bus or from the B bus to
the A bus. If both G
and GAB LOW), the outputs are in the high impedance
state and data is stored at the A and B busses. When G
is active LOW, B data is sent to the A bus. When GA B is
active HIGH, data from the A bu s is sent to the B bus. If
both enable inputs are active (G
B data is sent to the A bus while A data is sent to the B bus.
BA and GAB are disabl ed (GBA HIGH
BA LOW and GAB HIGH)
Function Table
Enable Inputs Operation
BA GAB 74F620 74F623
G
BA
LLB
HHA
HL Z Z
LHB
H = HIGH Voltage Level
L = LOW Voltage L ev el
Z = High Impedance
Data to A Bus B Data to A Bus
Data to B Bus A Data to B Bus
Data to A Bus, B Data to A Bus,
Data to B Bus A Data to B Bus
A
Logic Diagrams
74F620
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and shou ld not be used to estimate propagation delays.
74F623
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and shou ld not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
Pin Potential to Ground Pin −0.5V to +7.0V
V
CC
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
ESD Last Pa ssing Voltage (Min) 4000V
Conditions
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyon d which the device
CC
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
(mA)
DC Electrical Characteristics
74F620 • 74F623
Symbol Parameter Min Typ Max Units
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
BVIT
I
CEX
V
ID
I
OD
I
IL
IIH + I
IIL + I
I
OS
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins)
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown (I/O)
Output HIGH
Leakage Current
Input Leakage
Test All Other Pins Grounded
Output Leakage
Circuit Current All Other Pins Grounded
10% V
10% V
2.0 V Min IOH = −15 mA (An, Bn)
CC
CC
0.55 V Min IOL = 64 mA (An, Bn)
5.0 µAMaxVIN = 2.7V
7.0 µAMaxVIN = 7.0V (GBA, GAB)
0.5 mA Max VIN = 5.5V (An, Bn)
50 µAMaxV
4.75 V 0.0
3.75 µA0.0
Input LOW Current −0.6 mA Max VIN = 0.5V (Non I/O Pins)
Output Leakage Current 70 µAMaxV
OZH
Output Leakage Current −650 µAMaxV
OZL
Output Short-Circuit Current −100 −225 mA Max V
Bus Drainage Test 500 µA0.0VV
Power Supply Current (74F620) 82 mA Max VO = HIGH, VIN = 0.2V
Power Supply Current (74F620) 82 mA Max VO = LOW
Power Supply Current (74F620) 95 mA Max VO = HIGH Z
Power Supply Current (74F623) 65 mA Max VO = HIGH
Power Supply Current (74F623) 82 mA Max VO = LOW, VIN = 0.2V
Power Supply Current (74F623) 85 mA Max VO = HIGH Z
V
CC
OUT
Conditions
= V
CC
IID = 1.9 µA
V
= 150 mV
IOD
= 2.7V (An, Bn)
OUT
= 0.5V (An, Bn)
OUT
= 0V
OUT
= 5.25V
OUT
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AC Electrical Characteristics
Symbol Parameter
t
PLH
t
74F620 • 74F623
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay 2.5 7.5 2.0 8.0
A Input to B Output (74F620) 2.0 7.0 2.0 7.0
Propagation Delay 2.5 7.5 2.0 8.0
B Input to A Output (74F620) 2.0 7.0 2.0 7.0
Propagation Delay 1.5 6.5 1.5 7.5
A Input to B Output (74F623) 2.0 7.0 2.0 7.5
Propagation Delay 1.5 6.5 1.5 7.5
B Input to A Output (74F623) 2.0 7.0 2.0 7.5
Enable Time 2.0 7.0 2.0 8.0
GBA Input to A Output 2.5 8.0 2.0 8.5
Disable Time 1.5 6.5 1.5 7.5
GBA Input to A Output 1.0 5.5 1.0 5.5
Enable Time 2.0 7.5 2.0 8.5
GAB Input to B Output (74F620) 3.0 8.0 2.0 8.5
Disable Time 2.5 8.0 2.0 9.0
GAB Input to B Output (74F620) 2.0 7.5 2.0 8.0
Enable Time 2.0 7.5 2.0 8.5
GAB Input to B Output (74F623) 2.5 8.0 2.0 8.5
Disable Time 2.0 8.0 2.0 9.0
GAB Input to B Output (74F623) 2.0 8.0 2.0 8.0
TA = +25°CT
= 0°C to +70°C
A
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
Units
ns
ns
ns
ns
ns
ns
ns
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Physical Dimensions inches (millimeters) unless otherwise noted
74F620 • 74F623
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
74F620 • 74F623 Inverting Octal Bus Transceiver with 3-STATE Outputs
Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
2. A critical component in any compon ent of a lif e supp ort
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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