Datasheet 74F574SJX, 74F574SJ, 74F574SCX, 74F574SC, 74F574PC Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS009567 www.fairchildsemi.com

April 1988
Revised August 1999

74F574 Octal D-Type Flip-Flop with 3-STATE Outputs

74F574
Octal D-Type Flip-Flop with 3-STATE Outputs

General Description

The 74F574 is a high-speed, low power octal flip-flop with a
buffered common Clock (CP ) a nd a bu ffered com mo n Ou t­put Enable (OE

). The information presented to the D inputs
is stored in the flip-flops on the LOW-to-HIGH Clock (CP)
transition.

This device is functiona lly identical to the 74F374 exce pt
for the pinouts.

Features

■ Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors

■ Useful as input or output port for microprocessors

■ Functionally identical to 74F374

■ 3-STATE outputs for bus-oriented applications

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F574SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F574PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2

74F574

Unit Loading/Fan Out

Functional Description

The 74F574 con sists of eig ht edge- triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Outp ut Enable are com mon to
all flip-flops. The eight flip-flops will store th e state of their
individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE

) LOW, the contents of the

eight flip-flops ar e available at the outputs. When OE

is
HIGH, the outputs go to th e high impeda nce state. Op era­tion of the OE

input does not affect t he state of the flip-

flops.

Function Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance



= LOW-to-HIGH Transition

NC = No Change

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

D0–D

7

Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP Clock Pulse Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
OE

3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
O

0–O7

3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA)

Inputs Internal Outputs

Function

OE

CP D Q O

H H L NC Z Hold
HHH NC Z Hold
H



L L Z Load

H



H H Z Load

L



L L L Data Available

L



H H H Data Available
L H L NC NC No Change in Data
L H H NC NC No Change in Data

3 www.fairchildsemi.com

74F574

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

CC

Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output

in HIGH State (with V

CC

= 0V)

Standard Output −0.5V to V

CC

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

Free Air Ambi ent Temperat ure 0°C to +70°C
Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

V

CC

Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized as a LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

V

OH

Output HIGH 10% V

CC

2.5

VMin

IOH = −1 mA

Voltage 10% V

CC

2.4 IOH = −3 mA

5% V

CC

2.7 IOH = −1 mA

5% V

CC

2.7 IOH = −3 mA

V

OL

Output LOW

10% V

CC

0.5 V Min IOL = 24 mA

Voltage

I

IH

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

I

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

I

CEX

Output HIGH

50 µAMaxV

OUT

= V

CC

Leakage Current

V

ID

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

I

OD

Output Leakage

3.75 µA0.0

V

IOD

= 150 mV

Circuit Current All Other Pins Grounded

I

IL

Input LOW Current −0.6 mA Max VIN = 0.5V

I

OZH

Output Leakage Current 50 µAMaxV

OUT

= 2.7V

I

OZL

Output Leakage Current −50 µAMaxV

OUT

= 0.5V

I

OS

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

I

ZZ

Bus Drainage Test 500 µA0.0VV

OUT

= 5.25V

I

CCZ

Power Supply Current 55 86 mA Max VO = HIGH Z

www.fairchildsemi.com 4

74F574

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

A

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

f

MAX

Maximum Clock Frequency 100 60 70 MHz

t

PLH

Propagation Delay 2.5 5.3 8.5 2.5 9.5 2.5 8.5

ns

t

PHL

CP to O

n

2.55.38.52.59.52.58.5

t

PZH

Output Enable Time 3.0 5.5 9.0 2.5 10.5 2.5 10.0

ns

t

PZL

3.0 6.0 9.0 2.5 10.5 2.5 10.0

t

PHZ

Output Disable Time 1.5 3.3 5.5 1.5 7.0 1.5 6.5

t

PLZ

1.52.85.51.57.01.56.5

Symbol Parameter

TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

Min Max Min Max Min Max

tS(H) Set-up Time, HIGH or LOW 2.5 3.0 2.5

ns

tS(L) Dn to CP 2.0 2.5 2.0
tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0
tH(L) Dn to CP 2.0 2.0 2.0
tW(H) CP Pulse Width 5.0 5.0 5.0

ns

tW(L) HIGH or LOW 5.0 5.0 5.0

5 www.fairchildsemi.com

74F574

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

www.fairchildsemi.com 6

74F574 Octal D-Type Flip-Flop with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical component in any compon ent of a life supp ort
device or system whose failu re to perform can be rea­sonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com