Page 1
INTEGRATED CIRCUITS
74F569
4-bit bidirectional binary synchronous
counter (3-State)
Product specification 1996 Jan 05
IC15 Data Handbook
Page 2
Philips Semiconductors Product specification
74F5694-bit bidirectional binary synchronous counter (3-State)
FEA TURES
•4-bit bidirectional counting – binary counter
•Synchronous counting and loading
•Look ahead carry capability for easy cascading
•Preset capability for programmable operation
•Master Reset (MR) overrides all other inputs
•Synchronous Reset (SR) overrides counting and parallel loading
•Clock Carry (CC) output to be used as a clock for flip-flops,
register and counters
•3-State outputs for bus organized systems
DESCRIPTION
The 74F569 is a fully synchronous Up/Down binary counter. It
features preset capabilities for programmable operation, carry look
ahead for programmable operation, carry look ahead for easy
cascading, and U/D
maximum flexibility there are both Synchronous and Master Reset
inputs as well as both Clocked Carry (CC
outputs. All state changes except Master Reset are initiated by
rising edge of the clock. A High signal on the Output Enable (OE)
input forces the output buffers into the high impedance state but
does not prevent counting, resetting or parallel loading.
input to control the direction of counting. For
) and Terminal Count (TC)
PIN CONFIGURATION
VCC
U/D
CP
CEP
MR
SR
GND
1
2
D0
3
D1
4
D2
5
D3
6
7
9
20
19
18
17
16
15
14
138
12
1110
SF01072
TC
CC
OE
Q0
Q1
Q2
Q3
CET
PE
TYPICAL
TYPE TYPICAL f
MAX
SUPPLY CURRENT
(TOTAL)
74F569 115MHz 40mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
T
= 0°C to +70°C
amb
20-pin plastic DIP N74F569N SOT146-1
20-pin plastic SO N74F569D SOT163-1
PKG.
DWG. #
LOGIC SYMBOL
11
1
2
7
12
8
9
17
= Pin 20
V
CC
GND = Pin 10
PE
U/D
CP
CEP
CET
MR
SR
OE
3456
D
0D1D2D3
Q0Q1Q2Q
3
13141516
CC
TC
18
19
SF01056
LOGIC SYMBOL (IEEE/IEC)
17
1
2
12
7
9
11
8
3
4
5
6
CTR DIV 10
EN10
M1[UP]
M2[DOWN]
C5/1,4,7,8+/2,4,7,8–
Z6
G7
G8
5CT=0
M3[LOAD]
M4[COUNT]
CT=0
3,5D
1,7(CT=15)G9
6,7,8,9
2,7(CT=0)G9
10
18
19
16
15
14
13
SF01057
1996 Jan 05 853–0376 16193
2
Page 3
Philips Semiconductors Product specification
74F5694-bit bidirectional binary synchronous counter (3-State)
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
D0 - D3 Parallel data inputs 1.0/1.0 20µA/0.6mA
CEP Count Enable parallel input (active Low) 1.0/1.0 20µA/0.6mA
CET Count Enable Trickle input (active Low) 1.0/2.0 20µA/1.2mA
CP Clock input (active rising edge) 1.0/1.0 20µA/0.6mA
PE Parallel Enable input (active Low) 1.0/2.0 20µA/1.2mA
U/D Up/Down count control input 1.0/1.0 20µA/0.6mA
OE Output Enable input 1.0/1.0 20µA/0.6mA
MR Master Reset input (active Low) 1.0/1.0 20µA/0.6mA
SR Synchronous Reset (active Low) 1.0/1.0 20µA/0.6mA
TC Terminal count output (active Low) 50/33 1.0mA/20mA
CC Clocked carry output (active Low) 50/33 1.0mA/20mA
Q0 - Q3 Data outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
FUNCTIONAL DESCRIPTION
The 74F569 counts in the modulo-16 binary sequence. From
state 0 (LLLL) it will increment to 15 in the up mode; in the down
mode it will decrement from 15 to 0. The clock inputs of all flip-flops
are driven parallel through a clock buffer. All state changes (except
due to Master Reset) occur synchronously with the Low-to-High
transition of the Clock Pulse (CP
The circuit has five fundamental modes of operation, in order of
precedence: asynchronous reset, synchronous reset, parallel load,
count and hold. Six control inputs–Master Reset (MR
Reset (SR
Count Enable Parallel (CEP
determine the mode of operation, as shown in the Function Table.
A Low signal on MR
forces the flip-flop Q outputs Low. A Low signal on SR
counting and parallel loading and allows the Q output to go Low on
the next rising edge of CP. A Low signal on PE
and allows information on the parallel data (Dn) inputs to be loaded
into the flip-flops on the next rising edge of CP. With MR
PE
Conversely, a High signal on either CEP
The 74F569 uses edge-triggered flip-flops and changing the SR, PE,
CEP
cause errors, provided that the recommended setup and hold times,
with respect to the rising edge of CP, are observed. Two types of
outputs are provided as overflow/underflow indicators. The Terminal
Count (TC
Low, when the counter reaches zero in the down mode, or reaches
maximum 15 in the up mode
TC
presetting, or until U/D
), Count Enable Trickle (CET), Parallel Enable (PE),
overrides all other inputs and asynchronously
High, CEP and CET permit counting when both are Low.
, CET or U/D inputs when the CP is in either state does not
) output is normally High and goes Low provided CET is
will then remain Low until a state change occurs by counting or
or CET is changed.
) input.
), Synchronous
), and the Up/Down (U/D) input –
overrides
overrides counting
, SR, and
and CET inhibits counting.
To implement synchronous multistage counters, the connections
between the TC output and the CEP and CET inputs can provide
either slow or fast carry propagation. Figure 1 shows the
connections for a simple ripple carry, in which the clock period must
be longer than the CP to TC
cumulative CET
CET
to CP setup time of the last stage. This total delay plus setup
time sets the upper limit on clock frequency. For faster clock rates,
the carry look ahead connections in Figure 2 are recommended. In
this scheme the ripple delay through the intermediate stages
commences with the same clock that causes the first stage to tick
over from Max to Min in the up mode, or Min to Max in the down
mode, to start its final cycle. Since this takes 16 clocks to complete,
there is plenty of time for the ripple to progress through the
intermediate stages. The critical timing that limits the clock period is
the CP to TC
of the last stage. The TC
internal race conditions and is therefore not recommended for use
as a clock or asynchronous reset for flip-flops, register or counters.
For such applications, the Clocked Carry (CC
The CC
the CC
output will go Low, when the clock next goes Low and will
stay Low until the clock goes High again; as shown in the CC
Function Table. When the Output Enable (OE) is Low, the parallel
data outputs Q0–Q3 are active and follow the flip-flop Q outputs. A
High signal on OE
does not prevent counting, loading or resetting.
LOGIC EQUATIONS:
Count Enable=CEP
Up: TC
=Q0×Q1×Q2×Q3×(Up)×CET
Down: TC=Q0×Q1×Q2×Q3×(Down)×CET
to TC delays of the intermediate stages, plus the
delay of the first stage plus the CEP to CP setup time
output is normally High. When CEP, CET, and TC are Low,
forces Q0–Q3 to the High impedance state but
×CET×PE
delay of the first stage, plus the
output is subject to decoding spikes due to
) output is provided.
1996 Jan 05
3
Page 4
Philips Semiconductors Product specification
OPERATING MODE
Hold (do nothing)
74F5694-bit bidirectional binary synchronous counter (3-State)
COUNT
CP TO ALL STAGES
COUNT
CP TO ALL STAGES
CET
CP
CET
CP
STATE DIAGRAM
01234
15
14
13
TC
TC
LOW
COUNT DOWN
COUNT UP
CET TC CET TC CET TC CET TC
SF01059
Figure 1. Multistage Counter with Ripple Carry
CEP
CET TC
CEP
CET TC
CEP
CET TC
CEP
CET
SF01061
Figure 2. Multistage Counter with Look-Ahead Carry
CC FUNCTION TABLE
INPUTS OUTPUT
SR PE CEP CET TC* CP CC
5
6
7
89101112
SF01058
L X X X X X H
X L X X X X H
X X H X X X H
X X X H X X H
X X X X H X H
H H L L L
*=TC is generated internally
H = High voltage level
L = Low voltage level
X = Don’t care
= Low Pulse
FUNCTION TABLE
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
1996 Jan 05
INPUTS
MR SR PE CEP CET U/D CP
L X X X X X X Asynchronous reset
h l X X X X
h h l X X X
h h h l l h
h h h l l l
h H H H X X
h H H X H X
↑ Synchronous reset
↑
↑
↑
Parallel load
Count Up (increment)
Count Down (decrement)
X
X
4
Page 5
Philips Semiconductors Product specification
74F5694-bit bidirectional binary synchronous counter (3-State)
LOGIC DIAGRAM
17
OE
8
MR
SR
3
D
0
4
D
1
5
D
2
6
D
3
9
11
PE
DCPQ
RD
DCPQ
RD
DCPQ
RD
DCPQ
RD
16
Q
Q
Q
Q
Q
0
15
Q
1
14
Q
2
13
Q
3
VCC= Pin 20
GND = Pin 10
1996 Jan 05
CEP
CET
CP
U/D
7
12
2
1
19
TC
18
CC
SF01062
5
Page 6
Philips Semiconductors Product specification
I
Current a lied to out ut in Low out ut state
SYMBOL
PARAMETER
IOHHigh-level out ut current
IOLLow-level out ut current
NO TAG
VOHHigh-level out ut voltage
CC IL
VOLLow-level out ut voltage
CC IL
IILLow-level in ut current
V
MAX, V
5V
74F5694-bit bidirectional binary synchronous counter (3-State)
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
V
I
IN
V
OUT
T
T
CC
IN
OUT
amb
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to +V
pp
p
Operating free-air temperature range 0 to +70 °C
Storage temperature –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
V
V
V
I
T
CC
IH
IL
IK
amb
Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
Input clamp current –18 mA
p
p
Operating free-air temperature range 0 70 °C
PARAMETER RATING UNIT
CC
p
TC, CC 40 mA
Qn 48 mA
V
LIMITS UNIT
MIN NOM MAX
TC, CC –1 mA
Qn –3 mA
TC, CC 20 mA
Qn 24 mA
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS
VCC = MIN, VIL = MAX,
VIH = MIN, I
OH
= MAX
VCC = MIN, VIL = MAX,
VIH = MIN, I
=
CC
OL
= MAX
IK
= 0.
I
VCC = MAX, VO = 2.7V 50 µA
VCC = MAX, VO = 0.5V –50 µA
VCC = MAX –60 –150 mA
VCC = MAX
V
I
I
I
IH
I
OZH
I
OZL
I
OS
I
CC
p
p
IK
Input clamp voltage VCC = MIN, II = I
Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA
High-level input current VCC = MAX, VI = 2.7V 20 µA
p
Others
CET, PE
Off-state output current,
High-level voltage applied
Off-state output current,
High-level voltage applied
Short-circuit output current
Supply current (total)
NO TAG
I
CCH
I
CCL
I
CCZ
±10%V
±5%V
±10%V
±5%V
MIN
2.4 V
CC
2.7 3.3 V
CC
CC
CC
TYP
NO TAG
MAX
0.35 0.50 V
0.35 0.50 V
–0.73 –1.2 V
–0.6 mA
–1.2 mA
38 60 mA
43 62 mA
40 60 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
= 5V, T
CC
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
amb
= 25°C.
, the use of high-speed test apparatus and/or sample-and-hold
OS
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
tests should be performed last.
OS
UNIT
1996 Jan 05
6
Page 7
Philips Semiconductors Product specification
f
74F5694-bit bidirectional binary synchronous counter (3-State)
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
SYMBOL PARAMETER TEST CONDITIONS
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum clock
frequency
Propagation delay
CP to Qn (PE, High or Low)
Propagation delay
CP to TC
Propagation delay
CET to TC
Propagation delay
U/D to TC
Propagation delay
CP to CC
Propagation delay
CEP, CET to CC
Propagation delay
MR to Qn
Propagation delay
U/D to CC
Propagation delay
MR to TC, CC
Propagation delay
SR to CC
Propagation delay
PE to CC
Output Enable time to
High or Low level OE to Qn
Output Disable time to
High or Low level OE to Qn
Qn Waveform 1 100 115 90 MHz
CC, TC Waveform 2 50 65 45 MHz
Waveform 1
Waveform 2
Waveform 3
Waveform 4
Waveform 2
Waveform 2
Waveform 5 6.0 8.0 11.0 5.5 12.0 ns
Waveform 4
Waveform 5 8.0 11.0 15.0 7.5 16.0
Waveform 3
Waveform 3
Waveform 10
Waveform 11
Waveform 10
Waveform 11
= +25°C T
amb
VCC = +5.V VCC = +5.V ± 10%
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
3.0
4.0
5.5
4.0
1.5
2.5
4.0
4.0
2.5
2.0
2.0
3.5
4.5
5.0
5.5
7.5
3.0
4.0
2.0
4.5
1.5
1.5
6.0
7.5
10.0
7.5
3.0
5.0
7.5
6.5
4.5
4.0
4.0
5.5
9.0
11.0
8.0
9.5
5.0
6.0
4.0
6.5
3.5
3.5
9.5
11.0
15.0
11.0
6.0
8.0
11.0
11.0
7.5
6.6
7.0
9.0
12.0
16.0
11.0
12.0
8.0
8.5
7.0
9.5
6.5
6.0
= 0°C to +70°C
amb
3.0
4.0
5.5
4.0
1.0
2.5
4.0
4.0
2.0
2.0
1.5
3.0
4.0
5.0
5.0
7.0
2.5
4.0
2.0
4.0
1.5
1.5
10.0
12.0
16.0
12.0
7.0
9.0
12.0
12.0
6.0
7.0
7.5
10.0
13.5
17.0
12.0
13.0
8.5
9.5
7.5
10.0
7.5
6.5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1996 Jan 05
7
Page 8
Philips Semiconductors Product specification
74F5694-bit bidirectional binary synchronous counter (3-State)
AC SETUP REQUIREMENTS
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST CONDITIONS
VCC = +5.0V VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MIN MAX
ts(H)
ts(L)
th(H)
t
(L)
h
ts(H)
t
(L)
s
th(H)
th(L)
ts(H)
t
(L)
s
th(H)
th(L)
ts(H)
t
(L)
s
th(H)
t
(L)
h
ts(H)
t
(L)
s
th(H)
t
(L)
h
tw(H)
t
(L)
w
Setup time, High or Low
Dn to CP
Hold time, High or Low
D
to CP
n
Setup time, High or Low
CEP
or CET to CP
Hold time, High or Low
CEP or CET to CP
Setup time, High or Low
PE
to CP
Hold time, High or Low
PE to CP
Setup time, High or Low
U/D
to CP
Hold time, High or Low
U/D
to CP
Setup time, High or Low
SR
to CP
Hold time, High or Low
SR
to CP
CP Pulse width,
High or Low
Waveform 6
Waveform 6
Waveform 7
Waveform 7
Waveform 6
Waveform 6
Waveform 8
Waveform 8
Waveform 9
Waveform 9
Waveform 1
4.0
4.0
2.0
2.0
5.0
5.0
0
0
8.0
8.0
0
0
10.0
8.0
0
0
8.0
8.0
0
0
7.0
5.0
tw(H) MR Pulse width, Low Waveform 5 4.5 5.0 ns
t
REC
Recovery time, MR to CP Waveform 5 6.0 7.0 ns
= 0°C to +70°C
amb
4.5
4.5
2.5
2.5
6.0
6.0
0
0
9.0
9.0
0
0
12.5
8.0
0
0
9.0
9.0
0
0
8.0
6.0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC WAVEFORMS
For all waveforms, VM = 1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
CP
Q
V
M
tW(H)
t
PLH
n
V
M
tW(L)
V
M
V
M
t
PHL
V
M
SF01063
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
CP, CEP,
CET
CC
TC
V
M
t
PLH
Waveform 2. Propagation Delay, CP, CET,
and CEP
V
M
V
M
t
PHL
V
M
to CC and CP to TC
V
M
t
PHL
V
M
t
PLH
V
M
SF01064
1996 Jan 05
8
Page 9
Philips Semiconductors Product specification
74F5694-bit bidirectional binary synchronous counter (3-State)
AC WAVEFORMS (Continued)
For all waveforms, VM = 1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
CET, SR, PE
TC, CC
V
M
t
PHL
V
V
M
t
PLH
M
V
M
SF01065
Waveform 3. Propagation Delays CET to TC
and SR
or PE to CC
tW(L)
MR
t
REC
V
CP
Qn
t
PHL
V
M
M
SF01067
Waveform 5. Master Reset Pulse Width, Master Reset to
Output Delay and Master Reset to Clock Recovery Time
CET
CEP
V
V
M
M
ts(L)
th(L) th(H)
V
ts(H)
V
M
M
U/D
TC, CC
V
M
t
PHL
V
V
M
t
PLH
M
V
M
SF01066
Waveform 4. Propagation Delays U/D to TC and CC
DATA
V
M
STABLE
t
s
V
MVM
ts(L) ts(H)th = 0
V
M
V
M
t
h
VMV
M
th = 0
V
M
SF01068
PE
CP
D
n
Waveform 6. Parallel Data and Parallel Enable Setup
and Hold Times
U/D
V
V
M
M
ts(L)
th(L) th(H)
V
V
M
M
ts(H)
CP
Q
n
V
NO CHANGE
M
V
M
COUNT
V
M
V
Waveform 7. Count Enable Data Setup and Hold Times
CP
SR
V
ts(H)
M
V
V
M
M
V
M
ts(L)
V
M
th(L)th(H)
V
M
Waveform 9. Synchronous Reset Setup and Hold Times
1996 Jan 05
M
SF01071
NO
CHANGE
SF01069
CP
Q
n
V
M
COUNT DOWNCOUNT UP
Waveform 8. Up/Down Control Setup and Hold Times
OE
Qn
V
M
t
PZH
V
M
t
PHZ
V
M
Waveform 10. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
9
V
M
SF01070
VOH -0.3V
SF01084
0V
Page 10
Philips Semiconductors Product specification
74F5694-bit bidirectional binary synchronous counter (3-State)
AC WAVEFORMS (Continued)
For all waveforms, VM = 1.5V
The shaded areas indicate when the input is permitted to change for
predictable output performance.
OE
Qn
V
M
t
PZL
V
M
t
PLZ
V
M
+0.3V
V
OL
SF01083
Waveform 11. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
V
CC
R
V
PULSE
GENERATOR
IN
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
PLZ
t
PZL
closed
closed
All other open
V
D.U.T.
R
T
OUT
L
C
R
L
L
7.0V
NEGATIVE
PULSE
POSITIVE
PULSE
90%
10%
t
w
V
M
10%
)
t
THL (tf
)
t
TLH (tr
90%
V
M
t
w
Input Pulse Definition
t
TLH (tr
t
THL (tf
10%
)
)
90%
AMP (V)
90%
V
M
0V
AMP (V)
V
M
10%
0V
DEFINITIONS:
R
= Load resistor;
L
C
= Load capacitance includes jig and probe capacitance;
L
= Termination resistance should be equal to Z
R
T
1996 Jan 05
see AC electrical characteristics for value.
see AC electrical characteristics for value.
pulse generators.
OUT
of
family
74F
10
INPUT PULSE REQUIREMENTS
V
amplitude
3.0V
M
1.5V
rep. rate
1MHz 500ns
t
w
t
TLHtTHL
2.5ns 2.5ns
SF00777
Page 11
Philips Semiconductors Product specification
74F5694-bit bidirectional binary synchronous counter (3-State)
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
1996 Jan 05
11
Page 12
Philips Semiconductors Product specification
74F5694-bit bidirectional binary synchronous counter (3-State)
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
1996 Jan 05
12
Page 13
Philips Semiconductors Product specification
74F5694-bit bidirectional binary synchronous counter (3-State)
NOTES
1996 Jan 05
13
Page 14
Philips Semiconductors Product specification
74F5694-bit bidirectional binary synchronous counter (3-State)
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
(print code) Date of release: July 1994
Document order number: 9397-750-05139
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