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74F563
Octal D-Type Latch with 3-STATE Outputs
74F563 Octal D-Type Latch with 3-STATE Outputs
April 1988
Revised August 1999
General Description
The 74F563 is a hi gh- speed octal latch wi th bu ffered com mon Latch Enable (LE) and buffered common Output
Enable (OE
This device is function ally ident ical to th e 74F573 , but has
inverted outputs.
) inputs.
Features
■ Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
■ Useful as input or output port for microprocessors
■ Functionally identical to 74F573
Ordering Code:
Order Number Package Number Package Description
74F563SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F563SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F563PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Logic Symbols
IEEE/IEC
Connection Diagram
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Unit Loading/Fan Out
74F563
Pin Names Description
D0–D
7
LE Latch Enable Input (Active HIGH) 1.0/1.0 20 µA/−0.6 mA
OE
O
0–O7
U.L.
HIGH/LOW
Data Inputs 1.0/1.0 20 µA/−0.6 mA
3-STATE Output Ena ble Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
3-STATE Latch Outputs 150/40 (33.3) −3 mA/24 mA (20 mA)
Input I
Output I
IH/IIL
OH/IOL
Functional Description
The 74F563 contai ns eight D-type latches with 3-STATE
output buffers. When the La tch En able ( LE) inpu t is HI GH,
data on the D
the latches are transparent, i.e., a latch output will chang e
state each time i ts D input ch anges. W hen LE is L OW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transitio n
of LE. The 3-STATE buffers are controlled by the O utput
Enable (OE
bi-state mode. When OE
impedance mode but thi s does not interfere with entering
new data into the latches.
inputs enters the latches. In this co ndition
n
) input. When OE is LOW, the buffers are in the
is HIGH the buffers are in the high
Logic Diagram
Function Table
Inputs Internal Output Function
LE D Q O
OE
H X X X Z High Z
H H L H Z High Z
H H H L Z High Z
H L X NC Z Latched
L H L H H Transparent
L H H L L Transparent
L L X NC NC Latched
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and shou ld not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
Pin Potential to Ground Pin −0.5V to +7.0V
V
CC
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
Conditions
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
CC
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
(mA)
DC Electrical Characteristics
74F563
Symbol Parameter Min Typ Max Units
V
V
V
V
V
I
IH
I
BVI
I
CEX
V
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCL
I
CCZ
IH
IL
CD
OH
OL
ID
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
Output HIGH 10% V
Voltage 10% V
5% V
5% V
Output LOW
Voltage
10% V
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test All Other Pins Grounded
Output Leakage
Circuit Current All Other Pins Grounded
2.5
CC
2.4 IOH = −3 mA
CC
2.7 IOH = −1 mA
CC
2.7 IOH = −3 mA
CC
CC
0.5 V Min IOL = 24 mA
5.0 µAMaxVIN = 2.7V
7.0 µAMaxVIN = 7.0V
50 µAMaxV
4.75 V 0.0
3.75 µA0.0
Input LOW Current −0.6 mA Max VIN = 0.5V
Output Leakage Current 50 µAMaxV
Output Leakage Current −50 µAMaxV
Output Short-Circuit Current −60 −150 mA Max V
Bus Drainage Test 500 µA0.0VV
Power Supply Current 40 61 mA Max VO = LOW
Power Supply Current 40 61 mA Max VO = HIGH Z
V
CC
IOH = −1 mA
VMin
OUT
IID = 1.9 µA
V
IOD
OUT
OUT
OUT
OUT
Conditions
= V
CC
= 150 mV
= 2.7V
= 0.5V
= 0V
= 5.25V
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AC Electrical Characteristics
74F563
Symbol Parameter
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
Propagation Delay 3.5 8.5 3.0 10.5 3.0 9.5
Dn to O
n
Propagation Delay 4.5 9.5 4.0 11.0 4.0 10.5
LE to O
n
Output Enable Time 2.0 7.5 2.0 9.5 2.0 9.0
Output Disable Time 1.5 5.5 1.5 7.0 1.5 6.5
TA = +25°CT
VCC = +5.0V VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF CL = 50 pF
Min Typ Max Min Max Min Max
2.5 6.5 2.0 7.5 2.0 7.0
3.0 7.0 2.5 7.5 2.5 7.0
3.0 8.5 2.5 10.0 1.5 9.5
1.5 5.5 1.5 5.5 1.5 5.5
= −55°C to +125°CTA = 0°C to +70°C
A
AC Operating Requirements
TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C
Symbol Parameter
tS(H) Setup Time, HIGH or LOW 2.0 2.0 2.0
tS(L) Dn to LE 2.0 2.0 2.0
tH(H) Hold Time, HIGH or LOW 3.0 3.0 3.0
tH(L) Dn to LE 3.0 3.0 3.0
tW(H) LE Pulse Width, HIGH 4.0 4.0 4.0 ns
Min Max Min Max Min Max
Units
ns
ns
ns
UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V
ns
ns
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Physical Dimensions inches (millimeters) unless otherwise noted
74F563
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20B
Package Number M20D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
74F563 Octal D-Type Latch with 3-STATE Outputs
Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
2. A critical component in any compon ent of a lif e supp ort
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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